Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/52070 )
Change subject: arch: Implement StaticInst::advancePC(ThreadContext *) for
the ISAs.
......................................................................
arch: Implement StaticInst::advancePC(ThreadContext *) for the ISAs.
Change-Id: Icc0332eca55c38f80964e7f898ccfa35da64fdf9
---
M src/arch/arm/insts/static_inst.hh
M src/arch/x86/insts/microop.hh
M src/arch/x86/insts/static_inst.hh
M src/arch/power/insts/static_inst.hh
M src/arch/mips/isa/base.isa
M src/arch/arm/insts/macromem.hh
M src/arch/riscv/insts/static_inst.cc
M src/arch/riscv/insts/static_inst.hh
M src/arch/sparc/insts/micro.hh
M src/arch/arm/insts/mem.hh
M src/arch/arm/insts/mem64.hh
M src/arch/arm/insts/pred_inst.hh
M src/arch/arm/insts/vfp.hh
M src/arch/sparc/insts/static_inst.cc
M src/arch/sparc/insts/static_inst.hh
15 files changed, 184 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh
index 1dd69ea..90f12d2 100644
--- a/src/arch/arm/insts/macromem.hh
+++ b/src/arch/arm/insts/macromem.hh
@@ -44,6 +44,7 @@
#include "arch/arm/insts/pred_inst.hh"
#include "arch/arm/pcstate.hh"
#include "arch/arm/tlb.hh"
+#include "cpu/thread_context.hh"
namespace gem5
{
@@ -87,6 +88,20 @@
apc.advance();
}
}
+
+ void
+ advancePC(ThreadContext *tc) const override
+ {
+ PCState pc = tc->pcState().as<PCState>();
+ if (flags[IsLastMicroop]) {
+ pc.uEnd();
+ } else if (flags[IsMicroop]) {
+ pc.uAdvance();
+ } else {
+ pc.advance();
+ }
+ tc->pcState(pc);
+ }
};
class MicroOpX : public ArmStaticInst
@@ -109,6 +124,20 @@
apc.advance();
}
}
+
+ void
+ advancePC(ThreadContext *tc) const override
+ {
+ PCState pc = tc->pcState().as<PCState>();
+ if (flags[IsLastMicroop]) {
+ pc.uEnd();
+ } else if (flags[IsMicroop]) {
+ pc.uAdvance();
+ } else {
+ pc.advance();
+ }
+ tc->pcState(pc);
+ }
};
/**
diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh
index 4a2c8a0..d5ef424 100644
--- a/src/arch/arm/insts/mem.hh
+++ b/src/arch/arm/insts/mem.hh
@@ -43,6 +43,7 @@
#include "arch/arm/insts/pred_inst.hh"
#include "arch/arm/pcstate.hh"
+#include "cpu/thread_context.hh"
namespace gem5
{
@@ -69,6 +70,20 @@
apc.advance();
}
}
+
+ void
+ advancePC(ThreadContext *tc) const override
+ {
+ PCState pc = tc->pcState().as<PCState>();
+ if (flags[IsLastMicroop]) {
+ pc.uEnd();
+ } else if (flags[IsMicroop]) {
+ pc.uAdvance();
+ } else {
+ pc.advance();
+ }
+ tc->pcState(pc);
+ }
};
// The address is a base register plus an immediate.
diff --git a/src/arch/arm/insts/mem64.hh b/src/arch/arm/insts/mem64.hh
index e2dd5dd..53c0527 100644
--- a/src/arch/arm/insts/mem64.hh
+++ b/src/arch/arm/insts/mem64.hh
@@ -41,6 +41,7 @@
#include "arch/arm/insts/misc64.hh"
#include "arch/arm/insts/static_inst.hh"
#include "arch/arm/pcstate.hh"
+#include "cpu/thread_context.hh"
namespace gem5
{
@@ -87,6 +88,20 @@
apc.advance();
}
}
+
+ void
+ advancePC(ThreadContext *tc) const override
+ {
+ PCState pc = tc->pcState().as<PCState>();
+ if (flags[IsLastMicroop]) {
+ pc.uEnd();
+ } else if (flags[IsMicroop]) {
+ pc.uAdvance();
+ } else {
+ pc.advance();
+ }
+ tc->pcState(pc);
+ }
};
class Memory64 : public MightBeMicro64
diff --git a/src/arch/arm/insts/pred_inst.hh
b/src/arch/arm/insts/pred_inst.hh
index 1f62614..a4a6567 100644
--- a/src/arch/arm/insts/pred_inst.hh
+++ b/src/arch/arm/insts/pred_inst.hh
@@ -46,6 +46,7 @@
#include "base/compiler.hh"
#include "base/logging.hh"
#include "base/trace.hh"
+#include "cpu/thread_context.hh"
namespace gem5
{
@@ -400,6 +401,17 @@
else
apc.uAdvance();
}
+
+ void
+ advancePC(ThreadContext *tc) const override
+ {
+ PCState pc = tc->pcState().as<PCState>();
+ if (flags[IsLastMicroop])
+ pc.uEnd();
+ else
+ pc.uAdvance();
+ tc->pcState(pc);
+ }
};
} // namespace ArmISA
diff --git a/src/arch/arm/insts/static_inst.hh
b/src/arch/arm/insts/static_inst.hh
index e0b2ab5..290ff3c 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -52,6 +52,7 @@
#include "base/trace.hh"
#include "cpu/exec_context.hh"
#include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
#include "sim/byteswap.hh"
#include "sim/full_system.hh"
@@ -203,6 +204,14 @@
pcState.as<PCState>().advance();
}
+ void
+ advancePC(ThreadContext *tc) const override
+ {
+ PCState pc = tc->pcState().as<PCState>();
+ pc.advance();
+ tc->pcState(pc);
+ }
+
uint64_t getEMI() const override { return machInst; }
std::unique_ptr<PCStateBase>
diff --git a/src/arch/arm/insts/vfp.hh b/src/arch/arm/insts/vfp.hh
index 76b727e..e2409ac 100644
--- a/src/arch/arm/insts/vfp.hh
+++ b/src/arch/arm/insts/vfp.hh
@@ -45,6 +45,7 @@
#include "arch/arm/insts/misc.hh"
#include "arch/arm/pcstate.hh"
#include "arch/arm/regs/misc.hh"
+#include "cpu/thread_context.hh"
namespace gem5
{
@@ -866,6 +867,20 @@
}
}
+ void
+ advancePC(ThreadContext *tc) const override
+ {
+ PCState pc = tc->pcState().as<PCState>();
+ if (flags[IsLastMicroop]) {
+ pc.uEnd();
+ } else if (flags[IsMicroop]) {
+ pc.uAdvance();
+ } else {
+ pc.advance();
+ }
+ tc->pcState(pc);
+ }
+
float
fpSqrt (FPSCR fpscr,float x) const
{
diff --git a/src/arch/mips/isa/base.isa b/src/arch/mips/isa/base.isa
index cd13de2..8e9b50b 100644
--- a/src/arch/mips/isa/base.isa
+++ b/src/arch/mips/isa/base.isa
@@ -64,6 +64,14 @@
pc.as<PCState>().advance();
}
+ void
+ advancePC(ThreadContext *tc) const override
+ {
+ PCState pc = tc->pcState().as<PCState>();
+ pc.advance();
+ tc->pcState(pc);
+ }
+
std::unique_ptr<PCStateBase>
buildRetPC(const PCStateBase &cur_pc,
const PCStateBase &call_pc) const override
diff --git a/src/arch/power/insts/static_inst.hh
b/src/arch/power/insts/static_inst.hh
index eaa0100..3bac77e 100644
--- a/src/arch/power/insts/static_inst.hh
+++ b/src/arch/power/insts/static_inst.hh
@@ -33,6 +33,7 @@
#include "arch/power/types.hh"
#include "base/trace.hh"
#include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
namespace gem5
{
@@ -74,6 +75,14 @@
pc_state.as<PCState>().advance();
}
+ void
+ advancePC(ThreadContext *tc) const override
+ {
+ PCState pc = tc->pcState().as<PCState>();
+ pc.advance();
+ tc->pcState(pc);
+ }
+
std::unique_ptr<PCStateBase>
buildRetPC(const PCStateBase &cur_pc,
const PCStateBase &call_pc) const override
diff --git a/src/arch/riscv/insts/static_inst.cc
b/src/arch/riscv/insts/static_inst.cc
index ee8ab43..6f6b3fe 100644
--- a/src/arch/riscv/insts/static_inst.cc
+++ b/src/arch/riscv/insts/static_inst.cc
@@ -50,5 +50,17 @@
}
}
+void
+RiscvMicroInst::advancePC(ThreadContext *tc) const
+{
+ PCState pc = tc->pcState().as<PCState>();
+ if (flags[IsLastMicroop]) {
+ pc.uEnd();
+ } else {
+ pc.uAdvance();
+ }
+ tc->pcState(pc);
+}
+
} // namespace RiscvISA
} // namespace gem5
diff --git a/src/arch/riscv/insts/static_inst.hh
b/src/arch/riscv/insts/static_inst.hh
index ed180ed..ef8032d 100644
--- a/src/arch/riscv/insts/static_inst.hh
+++ b/src/arch/riscv/insts/static_inst.hh
@@ -36,6 +36,7 @@
#include "arch/riscv/types.hh"
#include "cpu/exec_context.hh"
#include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
#include "mem/packet.hh"
namespace gem5
@@ -64,6 +65,14 @@
pc.as<PCState>().advance();
}
+ void
+ advancePC(ThreadContext *tc) const override
+ {
+ PCState pc = tc->pcState().as<PCState>();
+ pc.advance();
+ tc->pcState(pc);
+ }
+
std::unique_ptr<PCStateBase>
buildRetPC(const PCStateBase &cur_pc,
const PCStateBase &call_pc) const override
@@ -139,6 +148,7 @@
}
void advancePC(PCStateBase &pcState) const override;
+ void advancePC(ThreadContext *tc) const override;
};
} // namespace RiscvISA
diff --git a/src/arch/sparc/insts/micro.hh b/src/arch/sparc/insts/micro.hh
index b07e8c2..8526cae 100644
--- a/src/arch/sparc/insts/micro.hh
+++ b/src/arch/sparc/insts/micro.hh
@@ -109,6 +109,17 @@
else
spc.uAdvance();
}
+
+ void
+ advancePC(ThreadContext *tc) const override
+ {
+ PCState pc = tc->pcState().as<PCState>();
+ if (flags[IsLastMicroop])
+ pc.uEnd();
+ else
+ pc.uAdvance();
+ tc->pcState(pc);
+ }
};
class SparcDelayedMicroInst : public SparcMicroInst
diff --git a/src/arch/sparc/insts/static_inst.cc
b/src/arch/sparc/insts/static_inst.cc
index d6da2b0..4f544f9 100644
--- a/src/arch/sparc/insts/static_inst.cc
+++ b/src/arch/sparc/insts/static_inst.cc
@@ -86,6 +86,14 @@
}
void
+SparcStaticInst::advancePC(ThreadContext *tc) const
+{
+ PCState pc = tc->pcState().as<PCState>();
+ pc.advance();
+ tc->pcState(pc);
+}
+
+void
SparcStaticInst::printSrcReg(std::ostream &os, int reg) const
{
if (_numSrcRegs > reg)
diff --git a/src/arch/sparc/insts/static_inst.hh
b/src/arch/sparc/insts/static_inst.hh
index c5cec25..3c1b73f 100644
--- a/src/arch/sparc/insts/static_inst.hh
+++ b/src/arch/sparc/insts/static_inst.hh
@@ -37,6 +37,7 @@
#include "base/trace.hh"
#include "cpu/exec_context.hh"
#include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
namespace gem5
{
@@ -112,6 +113,7 @@
const RegId *indexArray, int num) const;
void advancePC(PCStateBase &pcState) const override;
+ void advancePC(ThreadContext *tc) const override;
static bool passesFpCondition(uint32_t fcc, uint32_t condition);
static bool passesCondition(uint32_t codes, uint32_t condition);
diff --git a/src/arch/x86/insts/microop.hh b/src/arch/x86/insts/microop.hh
index 5fa0e37..9cbdec8 100644
--- a/src/arch/x86/insts/microop.hh
+++ b/src/arch/x86/insts/microop.hh
@@ -142,6 +142,17 @@
xpc.uAdvance();
}
+ void
+ advancePC(ThreadContext *tc) const override
+ {
+ PCState pc = tc->pcState().as<PCState>();
+ if (flags[IsLastMicroop])
+ pc.uEnd();
+ else
+ pc.uAdvance();
+ tc->pcState(pc);
+ }
+
std::unique_ptr<PCStateBase> branchTarget(
const PCStateBase &branch_pc) const override;
diff --git a/src/arch/x86/insts/static_inst.hh
b/src/arch/x86/insts/static_inst.hh
index d890904..176fc3d 100644
--- a/src/arch/x86/insts/static_inst.hh
+++ b/src/arch/x86/insts/static_inst.hh
@@ -42,6 +42,7 @@
#include "arch/x86/types.hh"
#include "base/trace.hh"
#include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
#include "debug/X86.hh"
namespace gem5
@@ -204,6 +205,14 @@
pcState.as<PCState>().advance();
}
+ void
+ advancePC(ThreadContext *tc) const override
+ {
+ PCState pc = tc->pcState().as<PCState>();
+ pc.advance();
+ tc->pcState(pc);
+ }
+
std::unique_ptr<PCStateBase>
buildRetPC(const PCStateBase &cur_pc,
const PCStateBase &call_pc) const override
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/52070
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icc0332eca55c38f80964e7f898ccfa35da64fdf9
Gerrit-Change-Number: 52070
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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