[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: Don't update stats in (read|set)Arch*Reg methods.

Wed, 27 Oct 2021 02:04:25 -0700

Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/51428 ) 

Change subject: cpu-o3: Don't update stats in (read|set)Arch*Reg methods.
......................................................................

cpu-o3: Don't update stats in (read|set)Arch*Reg methods.

These are called from the ThreadContext, and should not be counted in
the statistics. The (read|set)*Reg methods, aka readIntReg and not
readArchIntReg, are called from the (read|set)*RegOperand methods in the
DynInst, which is the ExecContext implementation when running on O3.

Change-Id: I9abf90fc7bbe80a742325b6dfd3c0e14392af54c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51428
Maintainer: Gabe Black <[email protected]>
Tested-by: kokoro <[email protected]>
Reviewed-by: Giacomo Travaglini <[email protected]>
---
M src/cpu/o3/cpu.cc
1 file changed, 26 insertions(+), 14 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 8f0c531..a574a4b 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1244,7 +1244,6 @@
 RegVal
 CPU::readArchIntReg(int reg_idx, ThreadID tid)
 {
-    cpuStats.intRegfileReads++;
     PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
             RegId(IntRegClass, reg_idx));

@@ -1254,7 +1253,6 @@
 RegVal
 CPU::readArchFloatReg(int reg_idx, ThreadID tid)
 {
-    cpuStats.fpRegfileReads++;
     PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
         RegId(FloatRegClass, reg_idx));

@@ -1266,7 +1264,7 @@
 {
     PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
                 RegId(VecRegClass, reg_idx));
-    return readVecReg(phys_reg);
+    return regFile.readVecReg(phys_reg);
 }

 TheISA::VecRegContainer&
@@ -1274,7 +1272,7 @@
 {
     PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
                 RegId(VecRegClass, reg_idx));
-    return getWritableVecReg(phys_reg);
+    return regFile.getWritableVecReg(phys_reg);
 }

 RegVal
@@ -1283,7 +1281,7 @@
 {
     PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
                                 RegId(VecElemClass, reg_idx, ldx));
-    return readVecElem(phys_reg);
+    return regFile.readVecElem(phys_reg);
 }

 const TheISA::VecPredRegContainer&
@@ -1291,7 +1289,7 @@
 {
     PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
                 RegId(VecPredRegClass, reg_idx));
-    return readVecPredReg(phys_reg);
+    return regFile.readVecPredReg(phys_reg);
 }

 TheISA::VecPredRegContainer&
@@ -1299,13 +1297,12 @@
 {
     PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
                 RegId(VecPredRegClass, reg_idx));
-    return getWritableVecPredReg(phys_reg);
+    return regFile.getWritableVecPredReg(phys_reg);
 }

 RegVal
 CPU::readArchCCReg(int reg_idx, ThreadID tid)
 {
-    cpuStats.ccRegfileReads++;
     PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
         RegId(CCRegClass, reg_idx));

@@ -1315,7 +1312,6 @@
 void
 CPU::setArchIntReg(int reg_idx, RegVal val, ThreadID tid)
 {
-    cpuStats.intRegfileWrites++;
     PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
             RegId(IntRegClass, reg_idx));

@@ -1325,7 +1321,6 @@
 void
 CPU::setArchFloatReg(int reg_idx, RegVal val, ThreadID tid)
 {
-    cpuStats.fpRegfileWrites++;
     PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
             RegId(FloatRegClass, reg_idx));

@@ -1338,7 +1333,7 @@
 {
     PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
                 RegId(VecRegClass, reg_idx));
-    setVecReg(phys_reg, val);
+    regFile.setVecReg(phys_reg, val);
 }

 void
@@ -1347,7 +1342,7 @@
 {
     PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
                 RegId(VecElemClass, reg_idx, ldx));
-    setVecElem(phys_reg, val);
+    regFile.setVecElem(phys_reg, val);
 }

 void
@@ -1356,13 +1351,12 @@
 {
     PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
                 RegId(VecPredRegClass, reg_idx));
-    setVecPredReg(phys_reg, val);
+    regFile.setVecPredReg(phys_reg, val);
 }

 void
 CPU::setArchCCReg(int reg_idx, RegVal val, ThreadID tid)
 {
-    cpuStats.ccRegfileWrites++;
     PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
             RegId(CCRegClass, reg_idx));


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51428
To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings 

Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9abf90fc7bbe80a742325b6dfd3c0e14392af54c
Gerrit-Change-Number: 51428
Gerrit-PatchSet: 5
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Daniel Carvalho <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Richard Cooper <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged

_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

Reply via email to