Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/52104 )
Change subject: arch,sim: Add a byteOrder accessor to the Workload class.
......................................................................
arch,sim: Add a byteOrder accessor to the Workload class.
The workload would have a better idea of what it's endianness is than
the system object that holds it. This is the first step towards getting
rid of the getByteOrder method on the system object, which currently
checks TARGET_ISA to determine what the default endianness should be.
If it makes sense for a Workload, it could determine the endianness
dynamically by, for instance, reading it out of a binary image before
putting it into memory.
This does assume that the workload has a consistent endianness
throughout which may not be true, but this is not a new assumption.
Also, mark the SEWorkload SimObject class as "abstract", since it isn't
useful until they get subclassed by some arch specific version.
Change-Id: I8d4ba8382f22236a81f9738cc3506cdb97bdbfb2
---
M src/arch/mips/linux/se_workload.hh
M src/arch/riscv/bare_metal/fs_workload.hh
M src/sim/workload.hh
M src/arch/x86/linux/se_workload.hh
M src/arch/power/linux/se_workload.hh
M src/arch/riscv/linux/se_workload.hh
M src/sim/kernel_workload.hh
M src/arch/riscv/linux/fs_workload.hh
M src/arch/sparc/linux/se_workload.hh
M src/arch/sparc/fs_workload.hh
M src/arch/arm/freebsd/se_workload.hh
M src/arch/arm/fs_workload.hh
M src/arch/x86/fs_workload.hh
M src/arch/arm/linux/se_workload.hh
M src/sim/Workload.py
15 files changed, 46 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/freebsd/se_workload.hh
b/src/arch/arm/freebsd/se_workload.hh
index a7f3453..8069bd2 100644
--- a/src/arch/arm/freebsd/se_workload.hh
+++ b/src/arch/arm/freebsd/se_workload.hh
@@ -55,6 +55,8 @@
EmuFreebsd(const Params &p) : SEWorkload(p, PageShift) {}
+ ByteOrder byteOrder() const override { return ByteOrder::little; }
+
struct BaseSyscallABI {};
struct SyscallABI32 : public SEWorkload::SyscallABI32,
public BaseSyscallABI
diff --git a/src/arch/arm/fs_workload.hh b/src/arch/arm/fs_workload.hh
index c917ffd..547bbf1 100644
--- a/src/arch/arm/fs_workload.hh
+++ b/src/arch/arm/fs_workload.hh
@@ -143,6 +143,8 @@
return loader::Arm64;
}
+ ByteOrder byteOrder() const override { return ByteOrder::little; }
+
FsWorkload(const Params &p);
void initState() override;
diff --git a/src/arch/arm/linux/se_workload.hh
b/src/arch/arm/linux/se_workload.hh
index 0ff08c7..b22688f 100644
--- a/src/arch/arm/linux/se_workload.hh
+++ b/src/arch/arm/linux/se_workload.hh
@@ -47,6 +47,7 @@
using Params = ArmEmuLinuxParams;
EmuLinux(const Params &p) : SEWorkload(p, PageShift) {}
+ ByteOrder byteOrder() const override { return ByteOrder::little; }
struct BaseSyscallABI {};
struct SyscallABI32 : public SEWorkload::SyscallABI32,
diff --git a/src/arch/mips/linux/se_workload.hh
b/src/arch/mips/linux/se_workload.hh
index c94112c..7e4d863 100644
--- a/src/arch/mips/linux/se_workload.hh
+++ b/src/arch/mips/linux/se_workload.hh
@@ -51,6 +51,7 @@
using Params = MipsEmuLinuxParams;
EmuLinux(const Params &p) : SEWorkload(p, PageShift) {}
+ ByteOrder byteOrder() const override { return ByteOrder::little; }
void syscall(ThreadContext *tc) override;
};
diff --git a/src/arch/power/linux/se_workload.hh
b/src/arch/power/linux/se_workload.hh
index 1b380ad..192147e 100644
--- a/src/arch/power/linux/se_workload.hh
+++ b/src/arch/power/linux/se_workload.hh
@@ -53,6 +53,8 @@
EmuLinux(const Params &p) : SEWorkload(p, PageShift) {}
+ ByteOrder byteOrder() const override { return ByteOrder::big; }
+
void syscall(ThreadContext *tc) override;
};
diff --git a/src/arch/riscv/bare_metal/fs_workload.hh
b/src/arch/riscv/bare_metal/fs_workload.hh
index 875910a..e10c0a0 100644
--- a/src/arch/riscv/bare_metal/fs_workload.hh
+++ b/src/arch/riscv/bare_metal/fs_workload.hh
@@ -64,6 +64,7 @@
}
loader::Arch getArch() const override { return bootloader->getArch(); }
+ ByteOrder byteOrder() const override { return ByteOrder::little; }
const loader::SymbolTable &
symtab(ThreadContext *tc) override
diff --git a/src/arch/riscv/linux/fs_workload.hh
b/src/arch/riscv/linux/fs_workload.hh
index f85ec16..cb29bee 100644
--- a/src/arch/riscv/linux/fs_workload.hh
+++ b/src/arch/riscv/linux/fs_workload.hh
@@ -53,6 +53,8 @@
KernelWorkload::setSystem(sys);
gdb = BaseRemoteGDB::build<RemoteGDB>(system);
}
+
+ ByteOrder byteOrder() const override { return ByteOrder::little; }
};
} // namespace RiscvISA
diff --git a/src/arch/riscv/linux/se_workload.hh
b/src/arch/riscv/linux/se_workload.hh
index bdc39ce..41a3d41 100644
--- a/src/arch/riscv/linux/se_workload.hh
+++ b/src/arch/riscv/linux/se_workload.hh
@@ -57,6 +57,8 @@
EmuLinux(const Params &p) : SEWorkload(p, PageShift) {}
+ ByteOrder byteOrder() const override { return ByteOrder::little; }
+
void syscall(ThreadContext *tc) override;
};
diff --git a/src/arch/sparc/fs_workload.hh b/src/arch/sparc/fs_workload.hh
index 06f02cf..90d5131 100644
--- a/src/arch/sparc/fs_workload.hh
+++ b/src/arch/sparc/fs_workload.hh
@@ -64,6 +64,7 @@
return pc;
}
loader::Arch getArch() const override { return loader::SPARC64; }
+ ByteOrder byteOrder() const override { return ByteOrder::big; }
const loader::SymbolTable &
symtab(ThreadContext *tc) override
diff --git a/src/arch/sparc/linux/se_workload.hh
b/src/arch/sparc/linux/se_workload.hh
index 01ab9b7..72bad47 100644
--- a/src/arch/sparc/linux/se_workload.hh
+++ b/src/arch/sparc/linux/se_workload.hh
@@ -58,6 +58,7 @@
EmuLinux(const Params &p);
loader::Arch getArch() const override { return loader::SPARC64; }
+ ByteOrder byteOrder() const override { return ByteOrder::big; }
void handleTrap(ThreadContext *tc, int trapNum) override;
void syscall(ThreadContext *tc) override;
diff --git a/src/arch/x86/fs_workload.hh b/src/arch/x86/fs_workload.hh
index 6c2038f..779e6ab 100644
--- a/src/arch/x86/fs_workload.hh
+++ b/src/arch/x86/fs_workload.hh
@@ -91,6 +91,8 @@
gdb = BaseRemoteGDB::build<RemoteGDB>(system);
}
+ ByteOrder byteOrder() const override { return ByteOrder::little; }
+
protected:
smbios::SMBiosTable *smbiosTable;
diff --git a/src/arch/x86/linux/se_workload.hh
b/src/arch/x86/linux/se_workload.hh
index 76db91f..85b0d69 100644
--- a/src/arch/x86/linux/se_workload.hh
+++ b/src/arch/x86/linux/se_workload.hh
@@ -68,6 +68,7 @@
}
loader::Arch getArch() const override { return loader::X86_64; }
+ ByteOrder byteOrder() const override { return ByteOrder::little; }
void syscall(ThreadContext *tc) override;
void event(ThreadContext *tc) override;
diff --git a/src/sim/Workload.py b/src/sim/Workload.py
index 92ed7c3..c881447 100644
--- a/src/sim/Workload.py
+++ b/src/sim/Workload.py
@@ -76,6 +76,7 @@
type = 'SEWorkload'
cxx_header = "sim/se_workload.hh"
cxx_class = 'gem5::SEWorkload'
+ abstract = True
@classmethod
def _is_compatible_with(cls, obj):
diff --git a/src/sim/kernel_workload.hh b/src/sim/kernel_workload.hh
index a1e8b98..503e6ea 100644
--- a/src/sim/kernel_workload.hh
+++ b/src/sim/kernel_workload.hh
@@ -84,6 +84,7 @@
KernelWorkload(const Params &p);
Addr getEntry() const override { return kernelObj->entryPoint(); }
+ ByteOrder byteOrder() const override { return
kernelObj->getByteOrder(); }
loader::Arch
getArch() const override
{
diff --git a/src/sim/workload.hh b/src/sim/workload.hh
index a57b6c1..9b3ef04 100644
--- a/src/sim/workload.hh
+++ b/src/sim/workload.hh
@@ -33,6 +33,7 @@
#include "base/loader/object_file.hh"
#include "base/loader/symtab.hh"
+#include "enums/ByteOrder.hh"
#include "params/StubWorkload.hh"
#include "params/Workload.hh"
#include "sim/sim_object.hh"
@@ -98,6 +99,7 @@
void startup() override;
virtual Addr getEntry() const = 0;
+ virtual ByteOrder byteOrder() const = 0;
virtual loader::Arch getArch() const = 0;
virtual const loader::SymbolTable &symtab(ThreadContext *tc) = 0;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8d4ba8382f22236a81f9738cc3506cdb97bdbfb2
Gerrit-Change-Number: 52104
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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