Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/52123 )
Change subject: arch-arm: Add partial param to TlbEntry
......................................................................
arch-arm: Add partial param to TlbEntry
The boolean will flag a partial translation
JIRA: https://gem5.atlassian.net/browse/GEM5-1108
Change-Id: Ia27e321cd5c4b062cafcfd0dc39a208a4d5e3247
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/pagetable.hh
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/pagetable.hh b/src/arch/arm/pagetable.hh
index 4cfdf2a..8300175 100644
--- a/src/arch/arm/pagetable.hh
+++ b/src/arch/arm/pagetable.hh
@@ -244,6 +244,8 @@
// This is used to distinguish between instruction and data entries
// in unified TLBs
TypeTLB type;
+ // True if the entry is caching a partial translation (a table walk)
+ bool partial;
// Type of memory
bool nonCacheable; // Can we wrap this in mtype?
@@ -266,6 +268,7 @@
domain(DomainType::Client), mtype(MemoryType::StronglyOrdered),
longDescFormat(false), isHyp(false), global(false), valid(true),
ns(true), nstid(true), el(EL0), type(TypeTLB::unified),
+ partial(false),
nonCacheable(uncacheable),
shareable(false), outerShareable(false), xn(0), pxn(0)
{
@@ -283,7 +286,7 @@
domain(DomainType::Client), mtype(MemoryType::StronglyOrdered),
longDescFormat(false), isHyp(false), global(false), valid(false),
ns(true), nstid(true), el(EL0), type(TypeTLB::unified),
- nonCacheable(false),
+ partial(false), nonCacheable(false),
shareable(false), outerShareable(false), xn(0), pxn(0)
{
// no restrictions by default, hap = 0x3
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia27e321cd5c4b062cafcfd0dc39a208a4d5e3247
Gerrit-Change-Number: 52123
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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