Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/52492 )
Change subject: python: Return a list of ISAs from get_runtime_isas.
......................................................................
python: Return a list of ISAs from get_runtime_isas.
The get_runtime_isas function is used in two contexts. The first is that
it lets a component specify that it requires support for a certain ISA
in order to work correctly. The second is a less direct way of checking
what the current targetted ISA is.
This change reworks get_runtime_isa to be get_runtime_isas which returns
a list of supported ISAs instead of a single ISA. This is still not
great because it depends on there being a single, universal list of what
ISAs exist, but at least it will give reasonable answers if there are
multiple ISAs configured.
The other use of get_runtime_isa, checking to see what type of ISA is
being simulated as a proxy for what type of ISA and what type of
components are being hooked up, is not as fixed by this change. That
assumption is still present, and will fall apart if multiple ISAs are
configured in, since the function will just tell you if an ISA is
supported, not if a particular system is using it.
Change-Id: I1fee85cc4297d8cb778b1fe5e951d9a4091fe6ca
---
M src/python/gem5/utils/requires.py
M
src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
M
src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py
M src/python/gem5/components/processors/simple_core.py
M tests/gem5/configs/boot_kvm_fork_run.py
M tests/gem5/configs/parsec_disk_run.py
M src/python/gem5/components/cachehierarchies/classic/no_cache.py
M tests/gem5/configs/boot_kvm_switch_exit.py
M
src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
M src/python/gem5/runtime.py
M
src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
M tests/gem5/configs/x86_boot_exit_run.py
12 files changed, 72 insertions(+), 56 deletions(-)
diff --git
a/src/python/gem5/components/cachehierarchies/classic/no_cache.py
b/src/python/gem5/components/cachehierarchies/classic/no_cache.py
index 11f6420..867f927 100644
--- a/src/python/gem5/components/cachehierarchies/classic/no_cache.py
+++ b/src/python/gem5/components/cachehierarchies/classic/no_cache.py
@@ -28,7 +28,7 @@
from ..abstract_cache_hierarchy import AbstractCacheHierarchy
from ...boards.abstract_board import AbstractBoard
from ....isas import ISA
-from ....runtime import get_runtime_isa
+from ....runtime import get_runtime_isas
from m5.objects import Bridge, BaseXBar, SystemXBar, BadAddr, Port
@@ -107,7 +107,7 @@
self.membus.cpu_side_ports, self.membus.cpu_side_ports
)
- if get_runtime_isa() == ISA.X86:
+ if ISA.X86 in get_runtime_isas():
int_req_port = self.membus.mem_side_ports
int_resp_port = self.membus.cpu_side_ports
core.connect_interrupt(int_req_port, int_resp_port)
diff --git
a/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
b/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
index f1fe5df..7f63c08 100644
---
a/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
+++
b/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
@@ -31,7 +31,7 @@
from .caches.mmu_cache import MMUCache
from ...boards.abstract_board import AbstractBoard
from ....isas import ISA
-from ....runtime import get_runtime_isa
+from ....runtime import get_runtime_isas
from m5.objects import Cache, BaseXBar, SystemXBar, BadAddr, Port
@@ -129,7 +129,7 @@
self.iptw_caches[i].cpu_side, self.dptw_caches[i].cpu_side
)
- if get_runtime_isa() == ISA.X86:
+ if ISA.X86 in get_runtime_isas():
int_req_port = self.membus.mem_side_ports
int_resp_port = self.membus.cpu_side_ports
cpu.connect_interrupt(int_req_port, int_resp_port)
diff --git
a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
index 7c4e829..8de6bbf 100644
---
a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
+++
b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
@@ -33,7 +33,7 @@
from .caches.mmu_cache import MMUCache
from ...boards.abstract_board import AbstractBoard
from ....isas import ISA
-from ....runtime import get_runtime_isa
+from ....runtime import get_runtime_isas
from m5.objects import Cache, L2XBar, BaseXBar, SystemXBar, BadAddr, Port
@@ -166,7 +166,7 @@
self.iptw_caches[i].cpu_side, self.dptw_caches[i].cpu_side
)
- if get_runtime_isa() == ISA.X86:
+ if ISA.X86 in get_runtime_isas():
int_req_port = self.membus.mem_side_ports
int_resp_port = self.membus.cpu_side_ports
cpu.connect_interrupt(int_req_port, int_resp_port)
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
index 9d42365..ced7d84 100644
---
a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
+++
b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
@@ -30,7 +30,7 @@
from ....coherence_protocol import CoherenceProtocol
from ....isas import ISA
from ...boards.abstract_board import AbstractBoard
-from ....runtime import get_runtime_isa
+from ....runtime import get_runtime_isas
from ....utils.requires import requires
from .topologies.simple_pt2pt import SimplePt2Pt
@@ -106,7 +106,7 @@
core,
self._num_l2_banks,
cache_line_size,
- get_runtime_isa(),
+ get_runtime_isas()[0],
board.get_clock_domain(),
)
@@ -129,7 +129,7 @@
)
# Connect the interrupt ports
- if get_runtime_isa() == ISA.X86:
+ if ISA.X86 in get_runtime_isas():
int_req_port = cache.sequencer.interrupt_out_port
int_resp_port = cache.sequencer.in_ports
core.connect_interrupt(int_req_port, int_resp_port)
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py
b/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py
index 523ba49..56fe2ec 100644
---
a/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py
+++
b/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py
@@ -34,7 +34,7 @@
from ....coherence_protocol import CoherenceProtocol
from ....isas import ISA
from ....utils.override import overrides
-from ....runtime import get_runtime_isa
+from ....runtime import get_runtime_isas
from ....utils.requires import requires
@@ -93,7 +93,7 @@
network=self.ruby_system.network,
core=core,
cache_line_size=board.get_cache_line_size(),
- target_isa=get_runtime_isa(),
+ target_isa=get_runtime_isas()[0],
clk_domain=board.get_clock_domain(),
)
@@ -116,7 +116,7 @@
)
# Connect the interrupt ports
- if get_runtime_isa() == ISA.X86:
+ if ISA.X86 in get_runtime_isas():
int_req_port = cache.sequencer.interrupt_out_port
int_resp_port = cache.sequencer.in_ports
core.connect_interrupt(int_req_port, int_resp_port)
diff --git a/src/python/gem5/components/processors/simple_core.py
b/src/python/gem5/components/processors/simple_core.py
index 6c0d6a5..017ae87 100644
--- a/src/python/gem5/components/processors/simple_core.py
+++ b/src/python/gem5/components/processors/simple_core.py
@@ -25,7 +25,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from typing import Optional
-from ...runtime import get_runtime_isa
+from ...runtime import get_runtime_isas
from ..processors.abstract_core import AbstractCore
from .cpu_types import CPUTypes
@@ -94,7 +94,7 @@
# controller as we require it. Not sure how true this is in all
cases.
self.core.createInterruptController()
- if get_runtime_isa() == ISA.X86:
+ if ISA.X86 in get_runtime_isas():
if interrupt_requestor != None:
self.core.interrupts[0].pio = interrupt_requestor
self.core.interrupts[0].int_responder = interrupt_requestor
diff --git a/src/python/gem5/runtime.py b/src/python/gem5/runtime.py
index 924da67..60622cf 100644
--- a/src/python/gem5/runtime.py
+++ b/src/python/gem5/runtime.py
@@ -29,47 +29,36 @@
"""
from m5.defines import buildEnv
+import typing
from .isas import ISA
from .coherence_protocol import CoherenceProtocol
-def get_runtime_isa() -> ISA:
- """Gets the target ISA.
+def get_runtime_isas() -> typing.List[ISA]:
+ """Gets the ISAs gem5 has support for.
This can be inferred at runtime.
- :returns: The target ISA.
+ :returns: A list of the supported ISAs.
"""
- isa_map = {
- "sparc": ISA.SPARC,
- "mips": ISA.MIPS,
- "null": ISA.NULL,
- "arm": ISA.ARM,
- "x86": ISA.X86,
- "power": ISA.POWER,
- "riscv": ISA.RISCV,
- }
+ isas = []
if buildEnv['USE_ARM']:
- isa_str = 'arm'
- elif buildEnv['USE_MIPS']:
- isa_str = 'mips'
- elif buildEnv['USE_POWER']:
- isa_str = 'power'
- elif buildEnv['USE_RISCV']:
- isa_str = 'riscv'
- elif buildEnv['USE_SPARC']:
- isa_str = 'sparc'
- elif buildEnv['USE_X86']:
- isa_str = 'x86'
- elif buildEnv['USE_NULL']:
- isa_str = 'null'
- if isa_str not in isa_map.keys():
- raise NotImplementedError(
- "ISA '" + isa_str + "' not recognized."
- )
+ isas.append(ISA.ARM)
+ if buildEnv['USE_MIPS']:
+ isas.append(ISA.MIPS)
+ if buildEnv['USE_NULL']:
+ isas.append(ISA.NULL)
+ if buildEnv['USE_POWER']:
+ isas.append(ISA.POWER)
+ if buildEnv['USE_RISCV']:
+ isas.append(ISA.RISCV)
+ if buildEnv['USE_SPARC']:
+ isas.append(ISA.SPARC)
+ if buildEnv['USE_X86']:
+ isas.append(ISA.X86)
- return isa_map[isa_str]
+ return isas
def get_runtime_coherence_protocol() -> CoherenceProtocol:
diff --git a/src/python/gem5/utils/requires.py
b/src/python/gem5/utils/requires.py
index 76a8b41..3aa4f82 100644
--- a/src/python/gem5/utils/requires.py
+++ b/src/python/gem5/utils/requires.py
@@ -24,7 +24,7 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from ..runtime import get_runtime_coherence_protocol, get_runtime_isa
+from ..runtime import get_runtime_coherence_protocol, get_runtime_isas
from ..isas import ISA
from ..coherence_protocol import CoherenceProtocol
from typing import Optional
@@ -68,11 +68,11 @@
protocol do not match that of the current gem5 binary.
"""
- runtime_isa = get_runtime_isa()
+ runtime_isas = get_runtime_isas()
runtime_coherence_protocol = get_runtime_coherence_protocol()
kvm_available = os.access("/dev/kvm", mode=os.R_OK | os.W_OK)
- if isa_required != None and isa_required != runtime_isa:
+ if isa_required != None and not isa_required in runtime_isas:
raise Exception(
_get_exception_str(
msg="The current ISA is '{}'. Required: '{}'".format(
@@ -100,4 +100,4 @@
_get_exception_str(
msg="KVM is required but is unavaiable on this system"
)
- )
\ No newline at end of file
+ )
diff --git a/tests/gem5/configs/boot_kvm_fork_run.py
b/tests/gem5/configs/boot_kvm_fork_run.py
index e9f0172..c55573a 100644
--- a/tests/gem5/configs/boot_kvm_fork_run.py
+++ b/tests/gem5/configs/boot_kvm_fork_run.py
@@ -53,7 +53,7 @@
)
from gem5.resources.resource import Resource
from gem5.runtime import (
- get_runtime_coherence_protocol, get_runtime_isa
+ get_runtime_coherence_protocol, get_runtime_isas
)
from gem5.utils.requires import requires
@@ -227,7 +227,7 @@
# Begin running of the simulation. This will exit once the Linux system
boot
# is complete.
-print("Running with ISA: " + get_runtime_isa().name)
+print("Running with ISA: " + get_runtime_isas()[0].name)
print("Running with protocol: " + get_runtime_coherence_protocol().name)
print()
diff --git a/tests/gem5/configs/boot_kvm_switch_exit.py
b/tests/gem5/configs/boot_kvm_switch_exit.py
index 79f3d86..e58e3ad 100644
--- a/tests/gem5/configs/boot_kvm_switch_exit.py
+++ b/tests/gem5/configs/boot_kvm_switch_exit.py
@@ -43,7 +43,7 @@
)
from gem5.resources.resource import Resource
from gem5.runtime import (
- get_runtime_coherence_protocol, get_runtime_isa
+ get_runtime_coherence_protocol, get_runtime_isas
)
from gem5.utils.requires import requires
@@ -208,7 +208,7 @@
# Begin running of the simulation. This will exit once the Linux system
boot
# is complete.
-print("Running with ISA: " + get_runtime_isa().name)
+print("Running with ISA: " + get_runtime_isas()[0].name)
print("Running with protocol: " + get_runtime_coherence_protocol().name)
print()
diff --git a/tests/gem5/configs/parsec_disk_run.py
b/tests/gem5/configs/parsec_disk_run.py
index 401e88a..6558d38 100644
--- a/tests/gem5/configs/parsec_disk_run.py
+++ b/tests/gem5/configs/parsec_disk_run.py
@@ -49,7 +49,7 @@
from gem5.components.processors.cpu_types import CPUTypes
from gem5.isas import ISA
from gem5.runtime import (
- get_runtime_isa,
+ get_runtime_isas,
get_runtime_coherence_protocol,
)
from gem5.utils.requires import requires
@@ -248,7 +248,7 @@
command=command,
)
-print("Running with ISA: " + get_runtime_isa().name)
+print("Running with ISA: " + get_runtime_isas()[0].name)
print("Running with protocol: " + get_runtime_coherence_protocol().name)
print()
diff --git a/tests/gem5/configs/x86_boot_exit_run.py
b/tests/gem5/configs/x86_boot_exit_run.py
index fcd29e9..5fefcf4 100644
--- a/tests/gem5/configs/x86_boot_exit_run.py
+++ b/tests/gem5/configs/x86_boot_exit_run.py
@@ -33,7 +33,7 @@
from gem5.runtime import (
get_runtime_coherence_protocol,
- get_runtime_isa,
+ get_runtime_isas,
)
from gem5.utils.requires import requires
from gem5.components.boards.x86_board import X86Board
@@ -216,7 +216,7 @@
# Begin running of the simulation. This will exit once the Linux system
boot
# is complete.
-print("Running with ISA: " + get_runtime_isa().name)
+print("Running with ISA: " + get_runtime_isas()[0].name)
print("Running with protocol: " + get_runtime_coherence_protocol().name)
print()
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1fee85cc4297d8cb778b1fe5e951d9a4091fe6ca
Gerrit-Change-Number: 52492
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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