This is discussed here: https://gem5.atlassian.net/browse/GEM5-1058
The CPUs are ISA specific as used, and this makes that more explicit. It also makes it clear whether a CPU is supported with a particular ISA, since if it isn't, it's not possible to put it into a config without adding the plumbing. By having those ISA specific CPU variants, they just show up as options for --cpu-type which makes se.py usable without modification. It would be possible to make configs work with an option like --isa, but there are at least three problems with that sort of approach. First, we should move away from this swiss army knife approach to writing configs where it can do anything, and we try to figure out how to make it work with complicated logic in the config. It's not likely that someone doing research would need to be able to transparently switch from using X86 to using RISCV without changing their config. Second, while many of our existing configs are single ISA, that is not required. On this branch, you could write a config which uses all 6 ISAs simultaneously as different machines in the same simulation, or even as a single frankenstein machine. Practically speaking, that can be useful (or even necessary) if there are different types of devices talking to each other in a network, or if the main SOC or application processor uses one architecture, but then subcomponents like accelerators, peripherals, management processors, etc, use some other architecture. On modern systems, there are usually many additional CPUs tucked into all kinds of places running various firmwares, and they don't always use the same ISA as the user sees. Third, that perpetuates having a big drop down box with ISAs on it, as if ISAs were paint that could be applied to a system after it was constructed, and as if ISAs were single, well defined options which were completely defined by this one choice. There are many variations of ARM CPUs, x86 CPUs, etc, and in RISCV there are even supposedly many variations of the ISA itself, depending on what extensions are enabled. Which ISA you pick is more integral and more specific than we've treated it in our configs, and using a --isa option would continue to bake that in. That said, while I think having a --isa option has a lot of problems and is not a good practice, exactly how a config script decides what components to use is really up to that script. If we want to build some mechanism which uses tables or long if-then trees in functions to figure out how to build up a system with a given ISA, nothing here would stop that. Gabe On Mon, Nov 8, 2021 at 11:03 AM Bobby Bruce <[email protected]> wrote: > Looks good to me. > > Perhaps this is explained elsewhere, but what's the logic in coupling the > CPU Type (Timing, Atomic, o3) with the ISA? Why do we interact with this > like `--cpu-type=X86AtomicSimpleCPU` and not `--cpu-type AtomicSimpleCPU > --isa=X86`? Current CPU types are switchable during a simulation, so they > are a parameter that can change, but the simulation's ISA, I assume, will > always fixed for the entirety of a run. > > -- > Dr. Bobby R. Bruce > Room 3050, > Kemper Hall, UC Davis > Davis, > CA, 95616 > > web: https://www.bobbybruce.net > > > On Mon, Nov 8, 2021 at 8:40 AM Jason Lowe-Power via gem5-dev < > [email protected]> wrote: > >> This looks quite promising! Uploading a branch to gerrit is a good idea. >> >> A couple of notes: >> 1. We are going to have to be very careful with when/how we merge this >> and its effect on users. For instance, changing the CPU from >> "AtomicSimpleCPU" to "ArmAtomicSimpleCPU" will break many users' use cases. >> 2. I just noticed that there's something wrong with the Arm hello >> application: "Simulated exit code not 0! Exit code is 13" It looks like >> current develop also has this problem, but it's a bit worrying. I can't >> figure out why the hello application wouldn't exit with code 0... >> >> Cheers, >> Jason >> >> On Sun, Nov 7, 2021 at 5:38 PM Gabe Black via gem5-dev <[email protected]> >> wrote: >> >>> Build performance improvements: >>> >>> >>> Building all 6 ISAs separately. >>> >>> $ time scons build/ARM/gem5.opt build/MIPS/gem5.opt build/POWER/gem5.opt >>> build/RISCV/gem5.opt build/SPARC/gem5.opt build/X86/gem5.opt >>> >>> real 37m0.210s >>> user 764m20.963s >>> sys 46m18.113s >>> >>> $ du -sh build >>> 16G build >>> >>> >>> Building "ALL" which has all 6 ISAs enabled together. >>> >>> $ time scons build/ALL/gem5.opt >>> >>> real 10m28.289s >>> user 194m31.505s >>> sys 9m36.281s >>> >>> $ du -sh build >>> 4.2G build >>> >>> >>> Which is a build time reduction of about 72% on my system, and a build >>> directory size reduction of about 73%. >>> >>> Gabe >>> >>> On Sat, Nov 6, 2021 at 12:29 AM Gabe Black <[email protected]> wrote: >>> >>>> As mentioned in the other thread, I can upload this hash as a branch on >>>> gerrit if people want to try it out. >>>> >>>> Gabe >>>> >>>> $ git log --oneline origin/develop..multiarch | wc -l >>>> 203 >>>> >>>> $ build/ALL/gem5.opt configs/example/se.py >>>> --cpu-type=ArmAtomicSimpleCPU -c tests/test-progs/hello/bin/arm/linux/hello >>>> build/ALL/base/statistics.hh:280: warn: One of the stats is a legacy >>>> stat. Legacy stat is a stat that does not belong to any statistics::Group. >>>> Legacy stat is deprecated. >>>> gem5 Simulator System. http://gem5.org >>>> gem5 is copyrighted software; use the --copyright option for details. >>>> >>>> gem5 version [DEVELOP-FOR-V21.2] >>>> gem5 compiled Nov 6 2021 00:23:55 >>>> gem5 started Nov 6 2021 00:25:58 >>>> gem5 executing on cake, pid 999191 >>>> command line: build/ALL/gem5.opt configs/example/se.py >>>> --cpu-type=ArmAtomicSimpleCPU -c tests/test-progs/hello/bin/arm/linux/hello >>>> >>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports` >>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports` >>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports` >>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports` >>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports` >>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports` >>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports` >>>> Global frequency set at 1000000000000 ticks per second >>>> build/ALL/mem/mem_interface.cc:791: warn: DRAM device capacity (8192 >>>> Mbytes) does not match the address range assigned (512 Mbytes) >>>> 0: system.remote_gdb: listening for remote gdb on port 7000 >>>> **** REAL SIMULATION **** >>>> build/ALL/sim/simulate.cc:194: info: Entering event queue @ 0. >>>> Starting simulation... >>>> Hello world! >>>> Exiting @ tick 2916500 because exiting with last active thread context >>>> Simulated exit code not 0! Exit code is 13 >>>> >>>> >>>> >>>> [gblack@cake work]$ build/ALL/gem5.opt configs/example/se.py >>>> --cpu-type=X86AtomicSimpleCPU -c tests/test-progs/hello/bin/x86/linux/hello >>>> build/ALL/base/statistics.hh:280: warn: One of the stats is a legacy >>>> stat. Legacy stat is a stat that does not belong to any statistics::Group. >>>> Legacy stat is deprecated. >>>> gem5 Simulator System. http://gem5.org >>>> gem5 is copyrighted software; use the --copyright option for details. >>>> >>>> gem5 version [DEVELOP-FOR-V21.2] >>>> gem5 compiled Nov 6 2021 00:23:55 >>>> gem5 started Nov 6 2021 00:26:10 >>>> gem5 executing on cake, pid 999224 >>>> command line: build/ALL/gem5.opt configs/example/se.py >>>> --cpu-type=X86AtomicSimpleCPU -c tests/test-progs/hello/bin/x86/linux/hello >>>> >>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports` >>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports` >>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports` >>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports` >>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports` >>>> warn: membus.master is deprecated. `master` is now called >>>> `mem_side_ports` >>>> warn: membus.master is deprecated. `master` is now called >>>> `mem_side_ports` >>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports` >>>> Global frequency set at 1000000000000 ticks per second >>>> build/ALL/mem/mem_interface.cc:791: warn: DRAM device capacity (8192 >>>> Mbytes) does not match the address range assigned (512 Mbytes) >>>> 0: system.remote_gdb: listening for remote gdb on port 7000 >>>> **** REAL SIMULATION **** >>>> build/ALL/sim/simulate.cc:194: info: Entering event queue @ 0. >>>> Starting simulation... >>>> Hello world! >>>> Exiting @ tick 5943000 because exiting with last active thread context >>>> >>> _______________________________________________ >>> gem5-dev mailing list -- [email protected] >>> To unsubscribe send an email to [email protected] >>> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s >> >> _______________________________________________ >> gem5-dev mailing list -- [email protected] >> To unsubscribe send an email to [email protected] >> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > >
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