Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/52584 )
Change subject: misc: Replace master/slave terminology from BaseCPU.py
......................................................................
misc: Replace master/slave terminology from BaseCPU.py
In order to fix several regression failures [1] the master/slave
terminology in src/cpu/BaseCPU.py was reintroduced [2].
This patch is addressing the issue by providing 2 different
ways of connecting cpu ports:
*) connectBus: The method assumes an object with a bus interface is
passed as an argument, therefore it tries to bind cpu ports to the
bus.mem_side_ports and bus.cpu_side_ports
*) connectAllPorts: No assumption on the port owning device is made.
The method simply accepts ports as arguments which will be directly
connected to the peer cpu ports
This will be used for example by ruby Sequencers
[1]: https://gem5.atlassian.net/browse/GEM5-775
[2]: https://gem5-review.googlesource.com/c/public/gem5/+/34495
Change-Id: I715ab8471621d6e5eb36731d7eaefbedf9663a71
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M tests/configs/simple-atomic-mp-ruby.py
M tests/configs/simple-timing-mp-ruby.py
M tests/configs/o3-timing-ruby.py
M tests/configs/t1000-simple-atomic.py
M src/cpu/testers/traffic_gen/BaseTrafficGen.py
M tests/configs/simple-timing-ruby.py
M tests/gem5/configs/base_config.py
M configs/common/CacheConfig.py
M src/cpu/BaseCPU.py
M configs/splash2/run.py
M configs/example/fs.py
M tests/configs/o3-timing-mp-ruby.py
M configs/example/arm/devices.py
M tests/configs/gpu-ruby.py
M src/mem/ruby/system/Sequencer.py
15 files changed, 86 insertions(+), 34 deletions(-)
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index bd68465..b270a83 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -187,11 +187,14 @@
system.cpu[i].createInterruptController()
if options.l2cache:
- system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
+ system.cpu[i].connectAllPorts(
+ system.tol2bus.cpu_side_ports,
+ system.membus.cpu_side_ports, system.membus.mem_side_ports)
elif options.external_memory_system:
- system.cpu[i].connectUncachedPorts(system.membus)
+ system.cpu[i].connectUncachedPorts(
+ system.membus.cpu_side_ports, system.membus.mem_side_ports)
else:
- system.cpu[i].connectAllPorts(system.membus)
+ system.cpu[i].connectBus(system.membus)
return system
diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index 788c268..73aea59 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -150,7 +150,7 @@
self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain)
self.l2 = self._l2_type()
for cpu in self.cpus:
- cpu.connectCachedPorts(self.toL2Bus)
+ cpu.connectCachedPorts(self.toL2Bus.cpu_side_ports)
self.toL2Bus.mem_side_ports = self.l2.cpu_side
def addPMUs(self, ints, events=[]):
@@ -184,7 +184,7 @@
self.l2.mem_side = bus.cpu_side_ports
except AttributeError:
for cpu in self.cpus:
- cpu.connectCachedPorts(bus)
+ cpu.connectCachedPorts(bus.cpu_side_ports)
class AtomicCluster(CpuCluster):
diff --git a/configs/example/fs.py b/configs/example/fs.py
index a39d2b3..5c02c15 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -263,7 +263,7 @@
cpu_id=0)
drive_sys.cpu.createThreads()
drive_sys.cpu.createInterruptController()
- drive_sys.cpu.connectAllPorts(drive_sys.membus)
+ drive_sys.cpu.connectBus(drive_sys.membus)
if args.kernel is not None:
drive_sys.workload.object_file = binary(args.kernel)
diff --git a/configs/splash2/run.py b/configs/splash2/run.py
index d90c779..fc0acd4 100644
--- a/configs/splash2/run.py
+++ b/configs/splash2/run.py
@@ -210,7 +210,10 @@
cpu.addPrivateSplitL1Caches(L1(size = args.l1size, assoc = 1),
L1(size = args.l1size, assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
- cpu.connectAllPorts(system.toL2bus, system.membus)
+ cpu.connectAllPorts(
+ system.toL2bus.cpu_side_ports,
+ system.membus.cpu_side_ports,
+ system.membus.mem_side_ports)
# ----------------------
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index fb5cbe6..5573b57 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -186,21 +186,23 @@
def createInterruptController(self):
self.interrupts = [ArchInterrupts() for i in
range(self.numThreads)]
- def connectCachedPorts(self, bus):
+ def connectCachedPorts(self, in_ports):
for p in self._cached_ports:
- exec('self.%s = bus.slave' % p)
+ exec('self.%s = in_ports' % p)
- def connectUncachedPorts(self, bus):
+ def connectUncachedPorts(self, in_ports, out_ports):
for p in self._uncached_interrupt_response_ports:
- exec('self.%s = bus.master' % p)
+ exec('self.%s = out_ports' % p)
for p in self._uncached_interrupt_request_ports:
- exec('self.%s = bus.slave' % p)
+ exec('self.%s = in_ports' % p)
- def connectAllPorts(self, cached_bus, uncached_bus = None):
- self.connectCachedPorts(cached_bus)
- if not uncached_bus:
- uncached_bus = cached_bus
- self.connectUncachedPorts(uncached_bus)
+ def connectAllPorts(self, cached_in, uncached_in, uncached_out):
+ self.connectCachedPorts(cached_in)
+ self.connectUncachedPorts(uncached_in, uncached_out)
+
+ def connectBus(self, bus):
+ self.connectAllPorts(bus.cpu_side_ports,
+ bus.cpu_side_ports, bus.mem_side_ports)
def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
self.icache = ic
@@ -229,7 +231,7 @@
xbar=None):
self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
self.toL2Bus = xbar if xbar else L2XBar()
- self.connectCachedPorts(self.toL2Bus)
+ self.connectCachedPorts(self.toL2Bus.cpu_side_ports)
self.l2cache = l2c
self.toL2Bus.mem_side_ports = self.l2cache.cpu_side
self._cached_ports = ['l2cache.mem_side']
diff --git a/src/cpu/testers/traffic_gen/BaseTrafficGen.py
b/src/cpu/testers/traffic_gen/BaseTrafficGen.py
index 4bccaa1..ae4df35 100644
--- a/src/cpu/testers/traffic_gen/BaseTrafficGen.py
+++ b/src/cpu/testers/traffic_gen/BaseTrafficGen.py
@@ -108,15 +108,19 @@
def createInterruptController(self):
pass
- def connectCachedPorts(self, bus):
+ def connectCachedPorts(self, in_ports):
if hasattr(self, '_cached_ports') and (len(self._cached_ports) >
0):
for p in self._cached_ports:
- exec('self.%s = bus.cpu_side_ports' % p)
+ exec('self.%s = in_ports' % p)
else:
- self.port = bus.cpu_side_ports
+ self.port = in_ports
- def connectAllPorts(self, cached_bus, uncached_bus = None):
- self.connectCachedPorts(cached_bus)
+ def connectAllPorts(self, cached_in, uncached_in, uncached_out):
+ self.connectCachedPorts(cached_in)
+
+ def connectBus(self, bus):
+ self.connectAllPorts(bus.cpu_side_ports,
+ bus.cpu_side_ports, bus.mem_side_ports)
def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
self.dcache = dc
diff --git a/src/mem/ruby/system/Sequencer.py
b/src/mem/ruby/system/Sequencer.py
index 703c533..6a475eb 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -112,7 +112,8 @@
import m5.objects
assert(isinstance(cpu, m5.objects.BaseCPU))
# this connects all cpu mem-side ports to self.in_ports
- cpu.connectAllPorts(self)
+ cpu.connectAllPorts(
+ self.in_ports, self.in_ports, self.interrupt_out_port)
def connectIOPorts(self, piobus):
"""
diff --git a/tests/configs/gpu-ruby.py b/tests/configs/gpu-ruby.py
index fc8f478..1864156 100644
--- a/tests/configs/gpu-ruby.py
+++ b/tests/configs/gpu-ruby.py
@@ -301,7 +301,10 @@
# Tie the cpu cache ports to the ruby cpu ports and
# physmem, respectively
#
-cpu.connectAllPorts(system.ruby._cpu_ports[0])
+cpu.connectAllPorts(
+ system.ruby._cpu_ports[0].in_ports,
+ system.ruby._cpu_ports[0].in_ports,
+ system.ruby._cpu_ports[0].interrupt_out_port)
system.ruby._cpu_ports[0].mem_master_port = system.piobus.slave
# attach CU ports to Ruby
diff --git a/tests/configs/o3-timing-mp-ruby.py
b/tests/configs/o3-timing-mp-ruby.py
index b68c6d5..b17502f 100644
--- a/tests/configs/o3-timing-mp-ruby.py
+++ b/tests/configs/o3-timing-mp-ruby.py
@@ -45,7 +45,7 @@
for cpu in cpus:
# create the interrupt controller
cpu.createInterruptController()
- cpu.connectAllPorts(system.membus)
+ cpu.connectBus(system.membus)
# All cpus are associated with cpu_clk_domain
cpu.clk_domain = system.cpu_clk_domain
diff --git a/tests/configs/o3-timing-ruby.py
b/tests/configs/o3-timing-ruby.py
index ed81ed7..719eedb 100644
--- a/tests/configs/o3-timing-ruby.py
+++ b/tests/configs/o3-timing-ruby.py
@@ -45,7 +45,7 @@
system.physmem.port = system.membus.master
# create the interrupt controller
cpu.createInterruptController()
-cpu.connectAllPorts(system.membus)
+cpu.connectBus(system.membus)
# Connect the system port for loading of binaries etc
system.system_port = system.membus.slave
diff --git a/tests/configs/simple-atomic-mp-ruby.py
b/tests/configs/simple-atomic-mp-ruby.py
index 21cdf50..a14bf30 100644
--- a/tests/configs/simple-atomic-mp-ruby.py
+++ b/tests/configs/simple-atomic-mp-ruby.py
@@ -43,7 +43,7 @@
# add L1 caches
for cpu in cpus:
- cpu.connectAllPorts(system.membus)
+ cpu.connectBus(system.membus)
# All cpus are associated with cpu_clk_domain
cpu.clk_domain = system.cpu_clk_domain
diff --git a/tests/configs/simple-timing-mp-ruby.py
b/tests/configs/simple-timing-mp-ruby.py
index 4218495..899f18b 100644
--- a/tests/configs/simple-timing-mp-ruby.py
+++ b/tests/configs/simple-timing-mp-ruby.py
@@ -83,7 +83,10 @@
#
# Tie the cpu ports to the ruby cpu ports
#
- cpu.connectAllPorts(system.ruby._cpu_ports[i])
+ cpu.connectAllPorts(
+ system.ruby._cpu_ports[i].in_ports,
+ system.ruby._cpu_ports[i].in_ports,
+ system.ruby._cpu_ports[i].interrupt_out_port)
# -----------------------
# run simulation
diff --git a/tests/configs/simple-timing-ruby.py
b/tests/configs/simple-timing-ruby.py
index d0ef6c5..cc1697f 100644
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -87,7 +87,10 @@
# Tie the cpu cache ports to the ruby cpu ports and
# physmem, respectively
#
-cpu.connectAllPorts(system.ruby._cpu_ports[0])
+cpu.connectAllPorts(
+ system.ruby._cpu_ports[0].in_ports,
+ system.ruby._cpu_ports[0].in_ports,
+ system.ruby._cpu_ports[0].interrupt_out_port)
# -----------------------
# run simulation
diff --git a/tests/configs/t1000-simple-atomic.py
b/tests/configs/t1000-simple-atomic.py
index 90bf525..4152a6c 100644
--- a/tests/configs/t1000-simple-atomic.py
+++ b/tests/configs/t1000-simple-atomic.py
@@ -43,7 +43,7 @@
system.cpu = cpu
# create the interrupt controller
cpu.createInterruptController()
-cpu.connectAllPorts(system.membus)
+cpu.connectBus(system.membus)
# create the memory controllers and connect them, stick with
# the physmem name to avoid bumping all the reference stats
diff --git a/tests/gem5/configs/base_config.py
b/tests/gem5/configs/base_config.py
index 260324d..9496f41 100644
--- a/tests/gem5/configs/base_config.py
+++ b/tests/gem5/configs/base_config.py
@@ -122,8 +122,10 @@
if not cpu.switched_out:
self.create_caches_private(cpu)
cpu.createInterruptController()
- cpu.connectAllPorts(sha_bus if sha_bus != None else
system.membus,
- system.membus)
+ cached_bus = sha_bus if sha_bus != None else system.membus
+ cpu.connectAllPorts(cached_bus.cpu_side_ports,
+ system.membus.cpu_side_ports,
+ system.membus.mem_side_ports)
def init_kvm_cpus(self, cpus):
"""
@@ -191,7 +193,7 @@
for i, cpu in enumerate(system.cpu):
if not cpu.switched_out:
cpu.createInterruptController()
- cpu.connectCachedPorts(system.ruby._cpu_ports[i])
+
cpu.connectCachedPorts(system.ruby._cpu_ports[i].in_ports)
else:
sha_bus = self.create_caches_shared(system)
for cpu in system.cpu:
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/52584
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I715ab8471621d6e5eb36731d7eaefbedf9663a71
Gerrit-Change-Number: 52584
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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