Mahyar Samani has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/52904 )
Change subject: stdlib: Updated MuliChannelMemory constructor
......................................................................
stdlib: Updated MuliChannelMemory constructor
This change updates the constructor for MultiChannelMemory. The
constructor now assumes every input parameter is of type string
and casts them to proper types inside the function. This way
the MultiChannelMemory could be tested easier. Considering that
tests might not want to pass in all the arguments and might use
argparser to read the inputs.
Change-Id: I80786066ccbb9cb1b7111831d9bc9d95e5204f40
---
M src/python/gem5/components/memory/multi_channel.py
1 file changed, 156 insertions(+), 11 deletions(-)
diff --git a/src/python/gem5/components/memory/multi_channel.py
b/src/python/gem5/components/memory/multi_channel.py
index 7d4baf1..26e856f 100644
--- a/src/python/gem5/components/memory/multi_channel.py
+++ b/src/python/gem5/components/memory/multi_channel.py
@@ -27,8 +27,8 @@
"""Multi channel "generic" DDR memory controllers
"""
-import enum
from math import log
+from warnings import warn
from ...utils.override import overrides
from m5.util.convert import toMemorySize
from ..boards.abstract_board import AbstractBoard
@@ -53,8 +53,8 @@
def __init__(
self,
dram_interface_class: Type[DRAMInterface],
- num_channels: int,
- interleaving_size: int,
+ num_channels: str,
+ interleaving_size: str,
size: Optional[str] = None,
addr_mapping: Optional[str] = None,
) -> None:
@@ -72,6 +72,42 @@
channel memory system. By default, it is equivalent to the atom
size, i.e., 64.
"""
+ # Make sure the input parameters are of the correct type
+ # Then cast them to the proper type they will be used
+ if not isinstance(num_channels, str):
+ warn(f"num_channels should be passed as a string. This could "
+ "cause an exception. num_channels will be cast to int.")
+ try:
+ num_channels = int(num_channels)
+ except:
+ raise Exception("Could not cast num_channels to int.")
+
+ if not isinstance(interleaving_size, str):
+ warn(f"interleaving_size should be passed as a string. This
could "
+ "cause an exception. interleaving_size will be cast to int.")
+ try:
+ interleaving_size = int(interleaving_size)
+ except:
+ raise Exception("Could not cast interleaving_size to int.")
+
+ if size:
+ if not isinstance(size, str):
+ warn(f"size should be passed as a string. This could
cause "
+ "an exception. size will be cast to string.")
+ try:
+ size = str(size)
+ except:
+ raise Exception("Could not cast size to str.")
+
+ if addr_mapping:
+ if not isinstance(addr_mapping, str):
+ warn(f"addr_mapping should be passed as a string. This
could "
+ "cause and exception. addr_mapping will be cast to
string.")
+ try:
+ addr_mapping = str(addr_mapping)
+ except:
+ raise Exception("Could not cast addr_mapping to str.")
+
super().__init__()
self._dram_class = dram_interface_class
self._num_channels = num_channels
@@ -98,7 +134,6 @@
MemCtrl(dram=self._dram[i]) for i in range(num_channels)
]
-
def _get_dram_size(self, num_channels: int, dram: DRAMInterface) ->
int:
return num_channels * (
dram.device_size.value
@@ -107,8 +142,10 @@
)
def _interleave_addresses(self):
- print(f"Memory is interleaving the address range {self._mem_range}"
- f" using {self._intlv_size} as interleaving size.")
+ print(
+ f"Memory is interleaving the address range {self._mem_range}"
+ f" using {self._intlv_size} as interleaving size."
+ )
if self._addr_mapping == "RoRaBaChCo":
rowbuffer_size = (
self._dram_class.device_rowbuffer_size.value
@@ -128,7 +165,7 @@
ctrl.dram.range = AddrRange(
start=self._mem_range.start,
end=self._mem_range.size(),
- intlvHighBit = intlv_low_bit + intlv_bits - 1,
+ intlvHighBit=intlv_low_bit + intlv_bits - 1,
xorHighBit=0,
intlvBits=intlv_bits,
intlvMatch=i,
@@ -137,10 +174,12 @@
@overrides(AbstractMemorySystem)
def incorporate_memory(self, board: AbstractBoard) -> None:
if self._intlv_size < int(board.get_cache_line_size()):
- raise ValueError("Memory interleaving size can not be smaller
than"
- " board's cache line size.\nBoard's cache line size: "
- f"{board.get_cache_line_size()}\n, This memory's interleaving "
- f"size: {self._intlv_size}")
+ raise ValueError(
+ "Memory interleaving size can not be smaller than"
+ " board's cache line size.\nBoard's cache line size: "
+ f"{board.get_cache_line_size()}\n, This memory's
interleaving "
+ f"size: {self._intlv_size}"
+ )
@overrides(AbstractMemorySystem)
def get_mem_ports(self) -> Sequence[Tuple[AddrRange, Port]]:
@@ -168,3 +207,93 @@
)
self._mem_range = ranges[0]
self._interleave_addresses()
+
+
+from .dram_interfaces.ddr3 import DDR3_1600_8x8, DDR3_2133_8x8
+from .dram_interfaces.ddr4 import DDR4_2400_8x8
+from .dram_interfaces.lpddr3 import LPDDR3_1600_1x32
+from .dram_interfaces.hbm import HBM_1000_4H_1x128
+
+
+def MultiChannelDDR3_1600(
+ num_channels: str,
+ interleaving_size: str,
+ size: Optional[str] = None,
+ address_mapping: Optional[str] = None,
+) -> AbstractMemorySystem:
+ """
+ A single channel memory system using a single DDR3_1600_8x8 based DIMM
+ """
+ return MultiChannelMemory(
+ DDR3_1600_8x8,
+ num_channels,
+ interleaving_size,
+ size=size,
+ addr_mapping=address_mapping,
+ )
+
+
+def MultiChannelDDR3_2133(
+ num_channels: str,
+ interleaving_size: str,
+ size: Optional[str] = None,
+ address_mapping: Optional[str] = None,
+) -> AbstractMemorySystem:
+ """
+ A single channel memory system using a single DDR3_2133_8x8 based DIMM
+ """
+ return MultiChannelMemory(
+ DDR3_2133_8x8,
+ num_channels,
+ interleaving_size,
+ size=size,
+ addr_mapping=address_mapping,
+ )
+
+
+def MultiChannelDDR4_2400(
+ num_channels: str,
+ interleaving_size: str,
+ size: Optional[str] = None,
+ address_mapping: Optional[str] = None,
+) -> AbstractMemorySystem:
+ """
+ A single channel memory system using a single DDR4_2400_8x8 based DIMM
+ """
+ return MultiChannelMemory(
+ DDR4_2400_8x8,
+ num_channels,
+ interleaving_size,
+ size=size,
+ addr_mapping=address_mapping,
+ )
+
+
+def MultiChannelLPDDR3_1600(
+ num_channels: str,
+ interleaving_size: str,
+ size: Optional[str] = None,
+ address_mapping: Optional[str] = None,
+) -> AbstractMemorySystem:
+ return MultiChannelMemory(
+ LPDDR3_1600_1x32,
+ num_channels,
+ interleaving_size,
+ size=size,
+ addr_mapping=address_mapping,
+ )
+
+
+def MultiChannelHBM(
+ num_channels: str,
+ interleaving_size: str,
+ size: Optional[str] = None,
+ address_mapping: Optional[str] = None,
+) -> AbstractMemorySystem:
+ return MultiChannelMemory(
+ HBM_1000_4H_1x128,
+ num_channels,
+ interleaving_size,
+ size=size,
+ addr_mapping=address_mapping,
+ )
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I80786066ccbb9cb1b7111831d9bc9d95e5204f40
Gerrit-Change-Number: 52904
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani <[email protected]>
Gerrit-MessageType: newchange
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