Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/52487 )
Change subject: cpu: Get rid of the BaseCPU UnifiedTLB parameter.
......................................................................
cpu: Get rid of the BaseCPU UnifiedTLB parameter.
This parameter is not (and as far as I can tell has never been) used,
and is guarded with a check of TARGET_ISA.
Change-Id: I71f4894228391e2024dab20e1bf2618dcea4f421
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52487
Reviewed-by: Giacomo Travaglini <[email protected]>
Maintainer: Giacomo Travaglini <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/cpu/BaseCPU.py
1 file changed, 16 insertions(+), 2 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index a9b490d..1fa4d9e 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -150,8 +150,6 @@
workload = VectorParam.Process([], "processes to run")
mmu = Param.BaseMMU(ArchMMU(), "CPU memory management unit")
- if buildEnv['TARGET_ISA'] == 'power':
- UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
interrupts = VectorParam.BaseInterrupts([], "Interrupt Controller")
isa = VectorParam.BaseISA([], "ISA instance")
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I71f4894228391e2024dab20e1bf2618dcea4f421
Gerrit-Change-Number: 52487
Gerrit-PatchSet: 7
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Bobby R. Bruce <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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