Bobby R. Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/52963 )
Change subject: stdlib: Fix RISCVBoard when running O3 CPU with Ruby
......................................................................
stdlib: Fix RISCVBoard when running O3 CPU with Ruby
The long/nightly tests were failing,
https://jenkins.gem5.org/job/nightly/47, due to a misconfiguration in
the RISCVBoard that caused a "fatal: Unable to find destination " error
when running the O3 CPU with a Ruby cache coherence protocol.
This patch resolves the issue by adding a "BadAddr" to handle bad
addresses occasionally produced by the O3 CPU.
Change-Id: I07fe06544e7588f45984032a022e73cd41d8a1e6
---
M src/python/gem5/components/boards/riscv_board.py
1 file changed, 20 insertions(+), 0 deletions(-)
diff --git a/src/python/gem5/components/boards/riscv_board.py
b/src/python/gem5/components/boards/riscv_board.py
index 8945f22..7c5b547 100644
--- a/src/python/gem5/components/boards/riscv_board.py
+++ b/src/python/gem5/components/boards/riscv_board.py
@@ -42,6 +42,7 @@
import m5
from m5.objects import (
+ BadAddr,
Bridge,
PMAChecker,
RiscvLinux,
@@ -107,6 +108,8 @@
# Incoherent I/O bus
self.iobus = IOXBar()
+ self.iobus.badaddr_responder = BadAddr()
+ self.iobus.default = self.iobus.badaddr_responder.pio
# The virtio disk
self.disk = RiscvMmioVirtIO(
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I07fe06544e7588f45984032a022e73cd41d8a1e6
Gerrit-Change-Number: 52963
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce <[email protected]>
Gerrit-MessageType: newchange
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