Alex Dutu has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/53067 )
Change subject: dev-amdgpu: Remove all copied linux headers
......................................................................
dev-amdgpu: Remove all copied linux headers
And create new headers with only the defines needed. The headers point
to the ROCm 4.2 source so we know where they came from. This is easier
than trying to get linux source through a scan and checking in to
public.
Change-Id: Ia7117999606009627d8c429dd443f13899b037d8
---
M src/dev/amdgpu/sdma_engine.cc
M src/dev/amdgpu/sdma_commands.hh
M src/dev/amdgpu/sdma_mmio.hh
D src/dev/amdgpu/vega10/soc15_ih_clientid.h
M src/dev/amdgpu/interrupt_handler.hh
M src/dev/amdgpu/amdgpu_vm.cc
M src/dev/amdgpu/amdgpu_vm.hh
7 files changed, 51 insertions(+), 97 deletions(-)
diff --git a/src/dev/amdgpu/amdgpu_vm.cc b/src/dev/amdgpu/amdgpu_vm.cc
index b245aaf..40ac3f4 100644
--- a/src/dev/amdgpu/amdgpu_vm.cc
+++ b/src/dev/amdgpu/amdgpu_vm.cc
@@ -253,7 +253,7 @@
range.size = std::min(range.size, next - range.vaddr);
range.paddr = range.vaddr - vm->getAGPBot() + vm->getAGPBase();
- printf("AMDGPUVM: AGP translation %#lx -> %#lx\n",
+ DPRINTF(AMDGPUDevice, "AMDGPUVM: AGP translation %#lx -> %#lx\n",
range.vaddr, range.paddr);
}
@@ -289,7 +289,7 @@
range.paddr = (bits(pte, 47, 12) << 12) | lower_bits;
}
- printf("AMDGPUVM: GART translation %#lx -> %#lx\n",
+ DPRINTF(AMDGPUDevice, "AMDGPUVM: GART translation %#lx -> %#lx\n",
range.vaddr, range.paddr);
}
@@ -305,7 +305,7 @@
range.size = std::min(range.size, next - range.vaddr);
range.paddr = range.vaddr - vm->getMMHUBBase();
- printf("AMDGPUVM: MMHUB translation %#lx -> %#lx\n",
+ DPRINTF(AMDGPUDevice, "AMDGPUVM: MMHUB translation %#lx -> %#lx\n",
range.vaddr, range.paddr);
}
@@ -315,7 +315,8 @@
// Get base address of the page table for this vmid
Addr base = vm->getPageTableBase(vmid);
Addr start = vm->getPageTableStart(vmid);
- printf("User tl base %#lx start %#lx walker %p\n", base, start,
walker);
+ DPRINTF(AMDGPUDevice, "User tl base %#lx start %#lx walker %p\n",
+ base, start, walker);
bool dummy;
unsigned logBytes;
diff --git a/src/dev/amdgpu/amdgpu_vm.hh b/src/dev/amdgpu/amdgpu_vm.hh
index b57b9ec..6c6c749 100644
--- a/src/dev/amdgpu/amdgpu_vm.hh
+++ b/src/dev/amdgpu/amdgpu_vm.hh
@@ -47,10 +47,10 @@
* MMIO offsets for graphics register bus manager (GRBM). These values were
* taken from linux header files. The header files can be found here:
*
- *
https://github.com/torvalds/linux/blob/master/drivers/gpu/drm/amd/include/
- * asic_reg/gc/gc_9_0_offset.h
- *
https://github.com/torvalds/linux/blob/master/drivers/gpu/drm/amd/include/
- * asic_reg/mmhub/mmhub_1_0_offset.h
+ * https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/rocm-4.2.0/
+ * drivers/gpu/drm/amd/include/ asic_reg/gc/gc_9_0_offset.h
+ * https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/rocm-4.2.0/
+ * drivers/gpu/drm/amd/include/ asic_reg/mmhub/mmhub_1_0_offset.h
*/
#define mmVM_INVALIDATE_ENG17_ACK
0x08c6
diff --git a/src/dev/amdgpu/interrupt_handler.hh
b/src/dev/amdgpu/interrupt_handler.hh
index 15a2c18..6324e0e 100644
--- a/src/dev/amdgpu/interrupt_handler.hh
+++ b/src/dev/amdgpu/interrupt_handler.hh
@@ -50,7 +50,25 @@
namespace gem5
{
-/*
+/**
+ * Defines from driver code. Taken from
+ * https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/rocm-4.2.0/
+ * drivers/gpu/drm/amd/include/soc15_ih_clientid.h
+ */
+enum soc15_ih_clientid
+{
+ SOC15_IH_CLIENTID_RLC = 0x07,
+ SOC15_IH_CLIENTID_SDMA0 = 0x08,
+ SOC15_IH_CLIENTID_SDMA1 = 0x09
+};
+
+enum ihSourceId
+{
+ TRAP_ID = 224
+};
+
+/**
+ * MSI-style interrupts. Send a "cookie" response to clear interrupts.
* From [1] we know the size of the struct is 8 dwords. Then we can look
at the register shift offsets in [2] to guess the rest.
* Or we can also look at [3].
*
@@ -80,6 +98,9 @@
uint32_t source_data_dw4;
} AMDGPUInterruptCookie;
+/**
+ * Struct to contain all interrupt handler related registers.
+ */
typedef struct
{
uint32_t IH_Cntl;
diff --git a/src/dev/amdgpu/sdma_commands.hh
b/src/dev/amdgpu/sdma_commands.hh
index ddebf5a..bbd7b92 100644
--- a/src/dev/amdgpu/sdma_commands.hh
+++ b/src/dev/amdgpu/sdma_commands.hh
@@ -37,8 +37,8 @@
/**
* Commands for the SDMA engine. The header files can be found here:
*
- *
https://github.com/torvalds/linux/blob/master/drivers/gpu/drm/amd/amdgpu/
- * vega10_sdma_pkt_open.h
+ * https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/rocm-4.2.0/
+ * drivers/gpu/drm/amd/amdgpu/vega10_sdma_pkt_open.h
*/
#define SDMA_OP_NOP 0
#define SDMA_OP_COPY 1
diff --git a/src/dev/amdgpu/sdma_engine.cc b/src/dev/amdgpu/sdma_engine.cc
index 806689c..e079f95 100644
--- a/src/dev/amdgpu/sdma_engine.cc
+++ b/src/dev/amdgpu/sdma_engine.cc
@@ -38,7 +38,6 @@
#include "dev/amdgpu/interrupt_handler.hh"
#include "dev/amdgpu/sdma_commands.hh"
#include "dev/amdgpu/sdma_mmio.hh"
-#include "dev/amdgpu/vega10/soc15_ih_clientid.h"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "params/SDMAEngine.hh"
diff --git a/src/dev/amdgpu/sdma_mmio.hh b/src/dev/amdgpu/sdma_mmio.hh
index 9595fb9..1faaa07 100644
--- a/src/dev/amdgpu/sdma_mmio.hh
+++ b/src/dev/amdgpu/sdma_mmio.hh
@@ -38,10 +38,10 @@
* MMIO offsets for SDMA engine. These values were taken from the linux
header
* for SDMA. The header files can be found here:
*
- *
https://github.com/torvalds/linux/blob/master/drivers/gpu/drm/amd/include/
- * asic_reg/sdma0/sdma0_4_0_offset.h
- *
https://github.com/torvalds/linux/blob/master/drivers/gpu/drm/amd/include/
- * asic_reg/sdma1/sdma1_4_0_offset.h
+ * https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/rocm-4.2.0/
+ * drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h
+ * https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/rocm-4.2.0/
+ * drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h
*/
#define mmSDMA_GFX_RB_CNTL 0x0080
#define mmSDMA_GFX_RB_BASE 0x0081
diff --git a/src/dev/amdgpu/vega10/soc15_ih_clientid.h
b/src/dev/amdgpu/vega10/soc15_ih_clientid.h
deleted file mode 100644
index c08ece1..0000000
--- a/src/dev/amdgpu/vega10/soc15_ih_clientid.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright 2018 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files
(the "Software"),
- * to deal in the Software without restriction, including without
limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef __SOC15_IH_CLIENTID_H__
-#define __SOC15_IH_CLIENTID_H__
-
-/*
- * src: https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/
- * 89baa3f89c8cb0d76e999c01bf304301e35abc9b/drivers/gpu/drm/amd/include/
- * soc15_ih_clientid.h
- */
-
- /*
- * vega10+ IH clients
- */
-enum soc15_ih_clientid {
- SOC15_IH_CLIENTID_IH = 0x00,
- SOC15_IH_CLIENTID_ACP = 0x01,
- SOC15_IH_CLIENTID_ATHUB = 0x02,
- SOC15_IH_CLIENTID_BIF = 0x03,
- SOC15_IH_CLIENTID_DCE = 0x04,
- SOC15_IH_CLIENTID_ISP = 0x05,
- SOC15_IH_CLIENTID_PCIE0 = 0x06,
- SOC15_IH_CLIENTID_RLC = 0x07,
- SOC15_IH_CLIENTID_SDMA0 = 0x08,
- SOC15_IH_CLIENTID_SDMA1 = 0x09,
- SOC15_IH_CLIENTID_SE0SH = 0x0a,
- SOC15_IH_CLIENTID_SE1SH = 0x0b,
- SOC15_IH_CLIENTID_SE2SH = 0x0c,
- SOC15_IH_CLIENTID_SE3SH = 0x0d,
- SOC15_IH_CLIENTID_SYSHUB = 0x0e,
- SOC15_IH_CLIENTID_UVD1 = 0x0e,
- SOC15_IH_CLIENTID_THM = 0x0f,
- SOC15_IH_CLIENTID_UVD = 0x10,
- SOC15_IH_CLIENTID_VCE0 = 0x11,
- SOC15_IH_CLIENTID_VMC = 0x12,
- SOC15_IH_CLIENTID_XDMA = 0x13,
- SOC15_IH_CLIENTID_GRBM_CP = 0x14,
- SOC15_IH_CLIENTID_ATS = 0x15,
- SOC15_IH_CLIENTID_ROM_SMUIO = 0x16,
- SOC15_IH_CLIENTID_DF = 0x17,
- SOC15_IH_CLIENTID_VCE1 = 0x18,
- SOC15_IH_CLIENTID_PWR = 0x19,
- SOC15_IH_CLIENTID_UTCL2 = 0x1b,
- SOC15_IH_CLIENTID_EA = 0x1c,
- SOC15_IH_CLIENTID_UTCL2LOG = 0x1d,
- SOC15_IH_CLIENTID_MP0 = 0x1e,
- SOC15_IH_CLIENTID_MP1 = 0x1f,
-
- SOC15_IH_CLIENTID_MAX,
-
- SOC15_IH_CLIENTID_VCN = SOC15_IH_CLIENTID_UVD
-};
-
-enum ihSourceId {
- TRAP_ID = 224
-};
-
-#endif
-
-
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia7117999606009627d8c429dd443f13899b037d8
Gerrit-Change-Number: 53067
Gerrit-PatchSet: 1
Gerrit-Owner: Alex Dutu <alexandru.d...@amd.com>
Gerrit-CC: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-MessageType: newchange
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