Jason Lowe-Power has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/54603 )
Change subject: misc: Add release notes for v21.2
......................................................................
misc: Add release notes for v21.2
Signed-off-by: Jason Lowe-Power <[email protected]>
Change-Id: Ia92440b3b2bcd777b75b0c65ab65252b27734ebb
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M RELEASE-NOTES.md
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+# Version 21.2.0.0
+
+## API (user-facing) changes
+
+All `SimObject` declarations in SConscript files now require the
`sim_objects` parameter which is a list of the
+`SimObjects` declared in that file.
+Anyone who has a non-upstream `SimObject` will need to update their
`SConscript` files.
+
+## Initial release of the "gem5 standard library"
+
+Previous release had an alpha release of the "components library."
+This has now been wrapped in a larger "standard library."
+
+The *gem5 standard library* is a Python package which contains the
following:
+
+- **Components:** A set of Python classes which wrap gem5's models. Some
of the components are preconfigured to match real hardware (e.g.,
`SingleChannelDDR3_1600`) and others are parameterized. Components can be
combined together onto *boards* which can be simulated.
+- **Resources:** A set of utilities to interact with the gem5-resources
repository/website. Using this module allows you to *automatically*
download and use many of gem5's prebuilt resources (e.g., kernels, disk
images, etc.).
+- **Simulate:** *THIS MODULE IS ALPHA!* A simpler interface to gem5's
simulation/run capabilities. Expect API changes to this module in future
releases. Feedback is appreciated.
+- **Prebuilt**: These are fully functioning prebuilt systems. These
systems are built from the components in `components`, but they have been
preconfigured with "known-good" parameters. This release has a "demo" board
to show an example of how to use the prebuilt systems.
+
+## Many Arm improvements
+
+- Improving configurability for Arm architectural extensions
(<https://gem5.atlassian.net/browse/GEM5-1132>)
+- Allow Arm TLB to store partial entries (walk cache)
(<https://gem5.atlassian.net/browse/GEM5-1108>)
+- Implement a multilevel TLB hierarchy
(<https://gem5.atlassian.net/browse/GEM5-790>)
+- Provide an Arm example script for the gem5-SST integration
(<https://gem5.atlassian.net/browse/GEM5-1121>)
+
+## GPU improvements
+
+- Improvements to the VIPER coherence protocol to fix bugs and improve
performance
+- VEGA GPU support added
+
+## gem5-SST bridges revived
+
+We now support gem5 cores connected to SST memory system for gem5 full
system mode.
+This has been tested for RISC-V and Arm.
+See `ext/sst/README.md` for details.
+
+## LupIO devices
+
+LupIO devices were developed by Prof. Joel Porquet-Lupine as a set of
open-source I/O devices to be used for teaching.
+They were designed to model a complete set of I/O devices that are neither
too complex to teach in a classroom setting, or too simple to translate to
understanding real-world devices.
+Our collection consists of a real-time clock, random number generator,
terminal device, block device, system controller, timer device,
programmable interrupt controller, as well as an inter-processor interrupt
controller.
+A more detailed outline of LupIO can be found here:
<https://luplab.cs.ucdavis.edu/assets/lupio/wcae21-porquet-lupio-paper.pdf>.
+Within gem5, these devices offer the capability to run simulations with a
complete set of I/O devices that are both easy to understand and manipulate.
+
+The initial implementation of the LupIO devices are for the RISC-V ISA.
+However, they should be simple to extend to other ISAs through small
source changes and updating the SConscripts.
+
+## Other improvements
+
+- Remove master/slave terminology: this was a closed ticket which was
marked as done even if there were multiple references of master/slave in
the config scripts which we fixed.
+- Armv8.2-A FEAT_UAO implementation
+- Implemented 'at' variants of file syscall in SE mode
(<https://gem5.atlassian.net/browse/GEM5-1098>)
+- Improved modularity in SConscripts
+- Arm atomic support in the CHI protocol
+- Many testing improvements
+- New "tester" CPU which mimics GPUS
+
# Version 21.1.0.2
**[HOTFIX]** [A commit introduced `std::vector` with `resize()` to
initialize all
storages](https://gem5-review.googlesource.com/c/public/gem5/+/27085).
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v21-2
Gerrit-Change-Id: Ia92440b3b2bcd777b75b0c65ab65252b27734ebb
Gerrit-Change-Number: 54603
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power <[email protected]>
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