Bobby Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/54923 )
Change subject: mem: Add 'controller()' function to NVMInterface.py
......................................................................
mem: Add 'controller()' function to NVMInterface.py
As noted here: https://gem5.atlassian.net/browse/GEM5-1133,
NVMInterface.py does not have a `controller()` function, which is used
by `configs/common/MemConfig.py` to obtain a memory control for a
specific memory type selected. This patch adds a `controller()`
function to `NVNInterface.py` to avoid the reported error.
It should be noted that we do not enforce a rule that a memory type
must include a `controller()` function. `se.py`, and other scrips
that use `configs/common/MemConfigs.py`, should not rely on this
false assumption.
Change-Id: Ieba62f803d3b9f9c5c3c863d5a8c4ca16c5e5e82
---
M src/mem/NVMInterface.py
1 file changed, 31 insertions(+), 0 deletions(-)
diff --git a/src/mem/NVMInterface.py b/src/mem/NVMInterface.py
index 5c8b27b..7c66901 100644
--- a/src/mem/NVMInterface.py
+++ b/src/mem/NVMInterface.py
@@ -35,6 +35,7 @@
from m5.params import *
from m5.proxy import *
+from m5.objects.MemCtrl import MemCtrl
from m5.objects.MemInterface import MemInterface
from m5.objects.DRAMInterface import AddrMap
@@ -65,6 +66,16 @@
two_cycle_rdwr = Param.Bool(False,
"Two cycles required to send read and write commands")
+
+ def controller(self):
+ """
+ Instantiate the memory controller and bind it to
+ the current interface.
+ """
+ controller = MemCtrl()
+ controller.nvm = self
+ return controller
+
# NVM delays and device architecture defined to mimic PCM like memory.
# Can be configured with DDR4_2400 sharing the channel
class NVM_2400_1x64(NVMInterface):
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ieba62f803d3b9f9c5c3c863d5a8c4ca16c5e5e82
Gerrit-Change-Number: 54923
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby Bruce <bbr...@ucdavis.edu>
Gerrit-MessageType: newchange
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