[gem5-dev] Change in gem5/gem5[develop]: cpu-simple: Convert invalid access assertions to fatal()

[Alex Richardson (Gerrit) via gem5-dev]

Alex Richardson has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55203 )

Change subject: cpu-simple: Convert invalid access assertions to fatal()
......................................................................

cpu-simple: Convert invalid access assertions to fatal()

Currently, an access to an invalid address will cause GEM5 to exit with
a `!pkt.isError()` assertion failure. I was seeing this assertion while
running a baremetal RISC-V binary that faulted before the trap vector
had been configured and therefore tried to jump to address zero. With
this change we now print the invalid address and the type of access
(ifetch/load/store/amo) which makes debugging such a problem much easier.
For example, my faulting program now prints the following:
`fatal: Instruction fetch ([0:0x4]) failed: BadAddressError [0:3] IF`
I also saw this assertion with a program that was dereferencing a NULL
pointer, which now prints a more helpful message:
`fatal: Data fetch ([0x10:0x11]) failed: BadAddressError [10:10]`

Change-Id: Id983b74bf4688711f47308c6c7c15f49662ac495
---
M src/cpu/simple/atomic.cc
1 file changed, 37 insertions(+), 5 deletions(-)



diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index d9738d2..92b90e7 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -406,7 +406,10 @@
             }
             dcache_access = true;

-            assert(!pkt.isError());
+            if (GEM5_UNLIKELY(pkt.isError())) {
+                fatal("Data fetch (%s) failed: %s",
+                        pkt.getAddrRange().to_string(), pkt.print());
+            }

             if (req->isLLSC()) {
                 thread->getIsaPtr()->handleLockedRead(req);
@@ -508,8 +511,10 @@
                     threadSnoop(&pkt, curThread);
                 }
                 dcache_access = true;
-                assert(!pkt.isError());
-
+                if (GEM5_UNLIKELY(pkt.isError())) {
+                    fatal("Data write (%s) failed: %s",
+                            pkt.getAddrRange().to_string(), pkt.print());
+                }
                 if (req->isSwap()) {
                     assert(res && curr_frag_id == 0);
                     memcpy(res, pkt.getConstPtr<uint8_t>(), size);
@@ -597,7 +602,10 @@

         dcache_access = true;

-        assert(!pkt.isError());
+        if (GEM5_UNLIKELY(pkt.isError())) {
+            fatal("Atomic access (%s) failed: %s",
+                    pkt.getAddrRange().to_string(), pkt.print());
+        }
         assert(!req->isLLSC());
     }

@@ -752,7 +760,10 @@
     pkt.dataStatic(decoder->moreBytesPtr());

     Tick latency = sendPacket(icachePort, &pkt);
-    assert(!pkt.isError());
+    if (GEM5_UNLIKELY(pkt.isError())) {
+        fatal("Instruction fetch (%s) failed: %s",
+                pkt.getAddrRange().to_string(), pkt.print());
+    }

     return latency;
 }

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id983b74bf4688711f47308c6c7c15f49662ac495
Gerrit-Change-Number: 55203
Gerrit-PatchSet: 1
Gerrit-Owner: Alex Richardson <alexrichard...@google.com>
Gerrit-MessageType: newchange
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