Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55249 )
Change subject: configs: WIP - Add a config for running DOS within gem5.
......................................................................
configs: WIP - Add a config for running DOS within gem5.
DOS or functional equivalent.
Tested with SeaBIOS so far, progress through BIOS startup, but no actual
booting, although also no bootable media set up.
The memory size detection falls back to the CMOS which is uninitialized,
so the BIOS's idea of memory size is bogus.
Change-Id: Ic27e0a5b5a0f513259694d592dde79a8826daaf7
---
A configs/example/dos.py
1 file changed, 151 insertions(+), 0 deletions(-)
diff --git a/configs/example/dos.py b/configs/example/dos.py
new file mode 100644
index 0000000..bebf493
--- /dev/null
+++ b/configs/example/dos.py
@@ -0,0 +1,135 @@
+# Copyright 2022
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import m5
+from m5.objects import *
+from m5.util import addToPath, fatal, warn
+
+addToPath('../')
+
+from common.SysPaths import binary
+
+# Constants similar to x86_traits.hh
+IO_address_space_base = 0x8000000000000000
+pci_config_address_space_base = 0xc000000000000000
+interrupts_address_space_base = 0xa000000000000000
+
+numCPUs = 1
+
+badaddr = BadAddr()
+membus = SystemXBar(
+ baddaddr=badaddr,
+ default=badaddr.pio,
+)
+
+iobus = IOXBar()
+bridge = Bridge(
+ delay='50ns',
+ mem_side_port=iobus.cpu_side_ports,
+ cpu_side_port=membus.mem_side_ports,
+)
+
+bridge.ranges = [
+ AddrRange(0xC0000000, 0xFFFF0000),
+ AddrRange(IO_address_space_base, interrupts_address_space_base - 1),
+ AddrRange(pci_config_address_space_base, Addr.max)
+]
+
+apicbridge = Bridge(
+ delay='50ns',
+ cpu_side_port = iobus.mem_side_ports,
+ mem_side_port = membus.cpu_side_ports,
+)
+
+APIC_range_size = 1 << 12
+apicbridge.ranges = [
+ AddrRange(interrupts_address_space_base,
+ interrupts_address_space_base + numCPUs * APIC_range_size -
1)
+]
+
+clk_domain = SrcClockDomain(
+ clock='1GHz',
+ voltage_domain=VoltageDomain(),
+)
+
+cpu = NonCachingSimpleCPU(cpu_id=0)
+
+cpu.createThreads()
+cpu.createInterruptController()
+cpu.connectBus(membus)
+
+bios_image_path = binary('bios.bin')
+bios = SimpleMemory(
+ image_file=bios_image_path,
+ port=membus.mem_side_ports,
+ range=AddrRange(0x100000000 - (64 * 1024), 0x100000000),
+ conf_table_reported=False,
+ in_addr_map=False,
+)
+
+bios_low = SimpleMemory(
+ image_file=bios_image_path,
+ port=membus.mem_side_ports,
+ range=AddrRange(0x100000 - (64 * 1024), 0x100000),
+ conf_table_reported=False,
+ in_addr_map=False,
+)
+
+conv_mem = SimpleMemory(
+ port=membus.mem_side_ports,
+ range=AddrRange(640 * 1024),
+)
+
+upper_mem = SimpleMemory(
+ port=membus.mem_side_ports,
+ range=AddrRange(768 * 1024, 960 * 1024),
+)
+
+system = System(
+ # Children
+ apicbridge=apicbridge,
+ bios=bios,
+ bridge=bridge,
+ conv_mem=conv_mem,
+ cpu=cpu,
+ iobus=iobus,
+ bios_low=bios_low,
+ membus=membus,
+ pc=Pc(),
+ upper_mem=upper_mem,
+
+ # Parameters
+ clk_domain=clk_domain,
+ mem_mode='atomic_noncaching',
+ system_port=membus.cpu_side_ports,
+ workload=X86BareMetalWorkload(),
+)
+
+system.pc.attachIO(iobus)
+
+root = Root(full_system=True, system=system)
+m5.instantiate()
+exit_event = m5.simulate()
+print('Exiting @ tick %i because %s' % (m5.curTick(),
exit_event.getCause()))
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic27e0a5b5a0f513259694d592dde79a8826daaf7
Gerrit-Change-Number: 55249
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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