I’m adding RISCV Vector extension support in Gem5 and I have a question about how to load up the source/dest vector registers used by the instructions.
The ISA parser generates code to load the source and target registers for an instruction depending on the strings it sees in the code block for that instruction in src/arch/riscv/isa/decoder.isa. The number of Vector registers accessed by each vector instruction is dependent on the values in the VTYPE CSR. For example, if VTYPE.LMUL is set to 4, and Rs1 is V0, the instruction will use V0-V4 as sources. >From my understanding, the ISA parser currently expects to find all the source and target registers that the insturction will use in the code block. This won’t work because we don’t know how many source/destination vector registers the instructions have till runtime. Any suggestions on what the right way is to get the parser to handle the vector registers? Jerin
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