Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55606 )
Change subject: arch-arm: Add a reverse map MiscRegIndex -> MiscRegNum64
......................................................................
arch-arm: Add a reverse map MiscRegIndex -> MiscRegNum64
Signed-off-by: Giacomo Travaglini <[email protected]>
Change-Id: I63cdcdfca610cfd37a03769e077388a193510bc7
---
M src/arch/arm/regs/misc.cc
M src/arch/arm/regs/misc.hh
2 files changed, 33 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index dd86bc4..47572ed 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -1454,6 +1454,10 @@
namespace {
+// The map is translating a MiscRegIndex into AArch64 system register
+// numbers (op0, op1, crn, crm, op2)
+std::unordered_map<MiscRegIndex, MiscRegNum64> idxToMiscRegNum;
+
// The map is translating AArch64 system register numbers
// (op0, op1, crn, crm, op2) into a MiscRegIndex
std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
@@ -1947,6 +1951,17 @@
}
}
+MiscRegNum64
+encodeAArch64SysReg(MiscRegIndex misc_reg)
+{
+ if (auto it = idxToMiscRegNum.find(misc_reg);
+ it != idxToMiscRegNum.end()) {
+ return it->second;
+ } else {
+ panic("Invalid MiscRegIndex: %n\n", misc_reg);
+ }
+}
+
void
ISA::initializeMiscRegMetadata()
{
@@ -4585,6 +4600,12 @@
// DBGDTRTX_EL0 -> DBGDTRRXint
// MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
+ // Populate the idxToMiscRegNum map
+ assert(idxToMiscRegNum.empty());
+ for (const auto& [key, val] : miscRegNumToIdx) {
+ idxToMiscRegNum.insert({val, key});
+ }
+
completed = true;
}
diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index ffa131d..1037f0e 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -1197,6 +1197,8 @@
MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1,
unsigned crn, unsigned crm,
unsigned op2);
+ MiscRegNum64 encodeAArch64SysReg(MiscRegIndex misc_reg);
+
// Whether a particular AArch64 system register is -always- read only.
bool aarch64SysRegReadOnly(MiscRegIndex miscReg);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I63cdcdfca610cfd37a03769e077388a193510bc7
Gerrit-Change-Number: 55606
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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