[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add a KvmKernelGicV3 model

Tue, 18 Jan 2022 05:31:46 -0800

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/55614 ) 

Change subject: arch-arm: Add a KvmKernelGicV3 model
......................................................................

arch-arm: Add a KvmKernelGicV3 model

JIRA: https://gem5.atlassian.net/browse/GEM5-1138

Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Change-Id: I7b0db0b8b436a6b2ca47444e4e1f8a2a20bd7c25
---
M src/arch/arm/kvm/KvmGic.py
M src/arch/arm/kvm/gic.cc
M src/arch/arm/kvm/gic.hh
M src/arch/arm/kvm/SConscript
4 files changed, 125 insertions(+), 3 deletions(-)



diff --git a/src/arch/arm/kvm/KvmGic.py b/src/arch/arm/kvm/KvmGic.py
index a192944..856befd 100644
--- a/src/arch/arm/kvm/KvmGic.py
+++ b/src/arch/arm/kvm/KvmGic.py
@@ -36,7 +36,7 @@
 from m5.params import *
 from m5.proxy import *

-from m5.objects.Gic import GicV2
+from m5.objects.Gic import GicV2, Gicv3

 class MuxingKvmGicV2(GicV2):
     type = 'MuxingKvmGicV2'
@@ -46,3 +46,12 @@

     simulate_gic = Param.Bool(False,

         "Forcing the simulation to use the gem5 GIC instead of the host  
GIC")

+
+class MuxingKvmGicV3(Gicv3):
+    type = 'MuxingKvmGicV3'
+    cxx_header = "arch/arm/kvm/gic.hh"
+    cxx_class = 'gem5::MuxingKvmGic<gem5::GicV3Types>'
+    cxx_template_params = [ 'class Types' ]
+
+    simulate_gic = Param.Bool(False,

+        "Forcing the simulation to use the gem5 GIC instead of the host  
GIC")

diff --git a/src/arch/arm/kvm/SConscript b/src/arch/arm/kvm/SConscript
index d06501f..f25ee96 100644
--- a/src/arch/arm/kvm/SConscript
+++ b/src/arch/arm/kvm/SConscript
@@ -44,7 +44,7 @@
     Return()

 SimObject('KvmGic.py',
-    sim_objects=['MuxingKvmGicV2'], tags='arm isa')
+    sim_objects=['MuxingKvmGicV2', 'MuxingKvmGicV3'], tags='arm isa')
 Source('gic.cc', tags='arm isa')


 SimObject('BaseArmKvmCPU.py', sim_objects=['BaseArmKvmCPU'], tags='arm  
isa')

diff --git a/src/arch/arm/kvm/gic.cc b/src/arch/arm/kvm/gic.cc
index 33a3f61..230fead 100644
--- a/src/arch/arm/kvm/gic.cc
+++ b/src/arch/arm/kvm/gic.cc
@@ -40,6 +40,7 @@
 #include <linux/kvm.h>

 #include "arch/arm/kvm/base_cpu.hh"
+#include "arch/arm/regs/misc.hh"
 #include "debug/GIC.hh"
 #include "debug/Interrupt.hh"
 #include "params/MuxingKvmGicV2.hh"
@@ -183,6 +184,60 @@
         KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_CPU, p.cpu_addr);
 }

+#ifndef SZ_64K
+#define SZ_64K 0x00000040
+#endif
+
+KvmKernelGicV3::KvmKernelGicV3(KvmVM &_vm,
+                               const MuxingKvmGicV3Params &p)
+    : KvmKernelGic(_vm, KVM_DEV_TYPE_ARM_VGIC_V3, p.it_lines),
+      redistRange(RangeSize(p.redist_addr, KVM_VGIC_V3_REDIST_SIZE)),
+      distRange(RangeSize(p.dist_addr, KVM_VGIC_V3_DIST_SIZE))
+{
+    kdev.setAttr<uint64_t>(

+        KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V3_ADDR_TYPE_DIST,  
p.dist_addr);

+    kdev.setAttr<uint64_t>(

+        KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V3_ADDR_TYPE_REDIST,  
p.redist_addr);

+}
+
+void
+KvmKernelGicV3::startup()
+{
+    kdev.setAttr<uint64_t>(
+        KVM_DEV_ARM_VGIC_GRP_CTRL, KVM_DEV_ARM_VGIC_CTRL_INIT, 0);
+}
+
+uint32_t
+KvmKernelGicV3::readRedistributor(ContextID ctx, Addr daddr)
+{
+    auto vcpu = vm.contextIdToVCpuId(ctx);

+    return getGicReg<uint32_t>(KVM_DEV_ARM_VGIC_GRP_REDIST_REGS, vcpu,  
daddr);

+}
+
+RegVal
+KvmKernelGicV3::readCpu(ContextID ctx, ArmISA::MiscRegIndex misc_reg)
+{
+    auto vcpu = vm.contextIdToVCpuId(ctx);
+    auto sys_reg = ArmISA::encodeAArch64SysReg(misc_reg).packed();

+    return getGicReg<RegVal>(KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, vcpu,  
sys_reg);

+}
+
+void

+KvmKernelGicV3::writeRedistributor(ContextID ctx, Addr daddr, uint32_t  
data)

+{
+    auto vcpu = vm.contextIdToVCpuId(ctx);

+    setGicReg<uint32_t>(KVM_DEV_ARM_VGIC_GRP_REDIST_REGS, vcpu, daddr,  
data);

+}
+
+void
+KvmKernelGicV3::writeCpu(ContextID ctx, ArmISA::MiscRegIndex misc_reg,
+                         RegVal data)
+{
+    auto vcpu = vm.contextIdToVCpuId(ctx);
+    auto sys_reg = ArmISA::encodeAArch64SysReg(misc_reg).packed();

+    setGicReg<RegVal>(KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, vcpu, sys_reg,  
data);

+}
+
 template <class Types>
 MuxingKvmGic<Types>::MuxingKvmGic(const Params &p)
   : GuestGic(p),
@@ -202,8 +257,10 @@
 {
     GuestGic::startup();
     usingKvm = (kernelGic != nullptr) && system.validKvmEnvironment();
-    if (usingKvm)
+    if (usingKvm) {
+        kernelGic->startup();
         fromGicToKvm();
+    }
 }

 template <class Types>
@@ -331,5 +388,6 @@
 }

 template class MuxingKvmGic<GicV2Types>;
+template class MuxingKvmGic<GicV3Types>;

 } // namespace gem5
diff --git a/src/arch/arm/kvm/gic.hh b/src/arch/arm/kvm/gic.hh
index 4ee048d..d082b2c 100644
--- a/src/arch/arm/kvm/gic.hh
+++ b/src/arch/arm/kvm/gic.hh
@@ -42,9 +42,11 @@
 #include "cpu/kvm/device.hh"
 #include "cpu/kvm/vm.hh"
 #include "dev/arm/gic_v2.hh"
+#include "dev/arm/gic_v3.hh"
 #include "dev/platform.hh"

 #include "params/MuxingKvmGicV2.hh"
+#include "params/MuxingKvmGicV3.hh"

 namespace gem5
 {
@@ -78,6 +80,8 @@
     KvmKernelGic &operator=(const KvmKernelGic &&rhs) = delete;
     KvmKernelGic &operator=(const KvmKernelGic &rhs) = delete;

+    virtual void startup() {}
+
   public:
     /**
      * @{
@@ -203,6 +207,38 @@

 };

+class KvmKernelGicV3 : public KvmKernelGic
+{
+  public:
+    /**
+     * Instantiate a KVM in-kernel GICv3 model.
+     *
+     * This constructor instantiates an in-kernel GICv3 model and wires
+     * it up to the virtual memory system.
+     *
+     * @param vm KVM VM representing this system
+     * @param params MuxingKvmGicV3 parameters
+     */
+    KvmKernelGicV3(KvmVM &vm,
+                   const MuxingKvmGicV3Params &params);
+
+    void startup() override;
+
+    /** BaseGicRegisters interface */
+    uint32_t readRedistributor(ContextID ctx, Addr daddr) override;
+    RegVal readCpu(ContextID ctx, ArmISA::MiscRegIndex misc_reg) override;
+
+    void writeRedistributor(ContextID ctx, Addr daddr,
+                            uint32_t data) override;
+    void writeCpu(ContextID ctx, ArmISA::MiscRegIndex misc_reg,
+                  RegVal data) override;
+  private:
+    /** Address range for the redistributor */
+    const AddrRange redistRange;
+    /** Address range for the distributor */
+    const AddrRange distRange;
+};
+
 struct GicV2Types
 {
     using GuestGic = GicV2;
@@ -210,6 +246,13 @@
     using Params = MuxingKvmGicV2Params;
 };

+struct GicV3Types
+{
+    using GuestGic = Gicv3;
+    using KvmGic = KvmKernelGicV3;
+    using Params = MuxingKvmGicV3Params;
+};
+
 template <class Types>
 class MuxingKvmGic : public Types::GuestGic
 {

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/55614

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7b0db0b8b436a6b2ca47444e4e1f8a2a20bd7c25
Gerrit-Change-Number: 55614
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange

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