Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55691 )
Change subject: arch-x86: Fix how flags registers are handled in IRET_REAL.
......................................................................
arch-x86: Fix how flags registers are handled in IRET_REAL.
There was a problem in how the data size worked, which could let data
leak through from the old value of a microcode register and affect the
new value of RFLAGS.
Change-Id: I2325bc3583b3c796c586c2ea4f6ba3cc56725077
---
M
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git
a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
index 2e7a2d1..525279c 100644
---
a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
+++
b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
@@ -56,9 +56,10 @@
# Update RFLAGS
# Get the current RFLAGS
- rflags t4
+ rflags t4, dataSize=8
# Flip flag bits if they should change.
- xor t5, t4, t3
+ mov t5, t4, t3
+ xor t5, t5, t4, dataSize=8
# Don't change VIF, VIP, or VM
limm t6, "~(VIFBit | VIPBit | VMBit)", dataSize=8
and t5, t5, t6, dataSize=8
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2325bc3583b3c796c586c2ea4f6ba3cc56725077
Gerrit-Change-Number: 55691
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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