Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55888 )
Change subject: arch-x86: Implement segment squashing in IRET.
......................................................................
arch-x86: Implement segment squashing in IRET.
In IRET when switching to a new CPL, if installed segments are not
conforming code segments and the new CPL would be less priveleged as the
descriptor's DPL, then those segments need to be set to null selectors.
Change-Id: Ie63f35e9d57cff270a1d7af35173f3e8e51c38e4
---
M
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
1 file changed, 90 insertions(+), 2 deletions(-)
diff --git
a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
index 7184849..bcc1622 100644
---
a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
+++
b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
@@ -223,14 +223,89 @@
andi t0, t7, 0x3, flags=(EZF,)
br label("skipSegmentSquashing"), flags=(CEZF,)
- # The attribute register needs to keep track of more info before this
will
- # work the way it needs to.
# FOR (seg = ES, DS, FS, GS)
# IF ((seg.attr.dpl < cpl && ((seg.attr.type = 'data')
# || (seg.attr.type = 'non-conforming-code')))
# {
# seg = NULL
# }
+ #
+ # t1 = temp_RIP (preserved but not used)
+ # t2 = Attr - [11:8] = type, [1:0] = dpl
+ # t3 = temp_RFLAGS (preserved but not used)
+ # t4 = handy m5 reg (preserved but not used)
+ # t5 = CPL
+ # t6 = 0xc00
+ # t7 = temp
+ #
+ # If the segment is data, bit 11 will be 0, and if it's conforming code
+ # then bit 11 will be 1 and 10 will be 0. That means that:
+ #
+ # (seg.attr.type = 'data') || (seg.attr.type = 'non-conforming-code')
+ #
+ # is the same as attr[11] == 0 || (attr[11] == 1 && attr[10] == 0)
which is
+ # the same as attr[11:10] != 11.
+
+ limm t6, 0xc00, dataSize=8
+
+ rdattr t2, ds, dataSize=8
+ # Check if attr[11:10] is 11.
+ xor t7, t2, t6, dataSize=8
+ and t0, t7, t6, flags=(EZF,), dataSize=8
+ br label("skipDSSquash"), flags=(CEZF,)
+ # Check if !(DPL < CPL)
+ andi t2, t2, 0x3, dataSize=8
+ sub t0, t2, t5, flags=(ECF,), dataSize=8
+ br label("skipDSSquash"), flags=(nCECF,)
+
+ wrdl ds, t0, t0
+ wrsel ds, t0
+
+skipDSSquash:
+
+ rdattr t2, es, dataSize=8
+ # Check if attr[11:10] is 11.
+ xor t7, t2, t6, dataSize=8
+ and t0, t7, t6, flags=(EZF,), dataSize=8
+ br label("skipESSquash"), flags=(CEZF,)
+ # Check if !(DPL < CPL)
+ andi t2, t2, 0x3, dataSize=8
+ sub t0, t2, t5, flags=(ECF,), dataSize=8
+ br label("skipESSquash"), flags=(nCECF,)
+
+ wrdl es, t0, t0
+ wrsel es, t0
+
+skipESSquash:
+
+ rdattr t2, fs, dataSize=8
+ # Check if attr[11:10] is 11.
+ xor t7, t2, t6, dataSize=8
+ and t0, t7, t6, flags=(EZF,), dataSize=8
+ br label("skipFSSquash"), flags=(CEZF,)
+ # Check if !(DPL < CPL)
+ andi t2, t2, 0x3, dataSize=8
+ sub t0, t2, t5, flags=(ECF,), dataSize=8
+ br label("skipFSSquash"), flags=(nCECF,)
+
+ wrdl fs, t0, t0
+ wrsel fs, t0
+
+skipFSSquash:
+
+ rdattr t2, gs, dataSize=8
+ # Check if attr[11:10] is 11.
+ xor t7, t2, t6, dataSize=8
+ and t0, t7, t6, flags=(EZF,), dataSize=8
+ br label("skipSegmentSquashing"), flags=(CEZF,)
+ # Check if !(DPL < CPL)
+ andi t2, t2, 0x3, dataSize=8
+ sub t0, t2, t5, flags=(ECF,), dataSize=8
+ br label("skipSegmentSquashing"), flags=(nCECF,)
+
+ wrdl gs, t0, t0
+ wrsel gs, t0
+
#}
skipSegmentSquashing:
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie63f35e9d57cff270a1d7af35173f3e8e51c38e4
Gerrit-Change-Number: 55888
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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