Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/49163 )
Change subject: arch-arm,cpu: Add a class for ops for vec reg elements.
......................................................................
arch-arm,cpu: Add a class for ops for vec reg elements.
This lets a caller print the name of a register in a friendly way
without having to know how many elements go with each vector register.
Change-Id: I85598c078c604f1bebdba797308102482639c209
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49163
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/arm/isa.cc
M src/cpu/reg_class.cc
M src/cpu/reg_class.hh
3 files changed, 41 insertions(+), 1 deletion(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index ed3bea2..5c8c743 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -80,6 +80,8 @@
}
} miscRegClassOps;
+VecElemRegClassOps vecRegElemClassOps(NumVecElemPerVecReg);
+
ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
_decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop),
afterStartup(false)
@@ -87,7 +89,8 @@
_regClasses.emplace_back(NUM_INTREGS, INTREG_ZERO);
_regClasses.emplace_back(0);
_regClasses.emplace_back(NumVecRegs);
- _regClasses.emplace_back(NumVecRegs * TheISA::NumVecElemPerVecReg);
+ _regClasses.emplace_back(NumVecRegs * NumVecElemPerVecReg,
+ vecRegElemClassOps);
_regClasses.emplace_back(NumVecPredRegs);
_regClasses.emplace_back(NUM_CCREGS);
_regClasses.emplace_back(NUM_MISCREGS, miscRegClassOps);
diff --git a/src/cpu/reg_class.cc b/src/cpu/reg_class.cc
index fc39e42..b667838 100644
--- a/src/cpu/reg_class.cc
+++ b/src/cpu/reg_class.cc
@@ -50,6 +50,14 @@
return csprintf("r%d", id.index());
}
+std::string
+VecElemRegClassOps::regName(const RegId &id) const
+{
+ RegIndex reg_idx = id.index() / elemsPerVec;
+ RegIndex elem_idx = id.index() % elemsPerVec;
+ return csprintf("v%d[%d]", reg_idx, elem_idx);
+}
+
const char *RegId::regClassStrings[] = {
"IntRegClass",
"FloatRegClass",
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index 3c3a656..da6be67 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -79,6 +79,19 @@
std::string regName(const RegId &id) const override;
};
+class VecElemRegClassOps : public RegClassOps
+{
+ protected:
+ size_t elemsPerVec;
+
+ public:
+ explicit VecElemRegClassOps(size_t elems_per_vec) :
+ elemsPerVec(elems_per_vec)
+ {}
+
+ std::string regName(const RegId &id) const override;
+};
+
class RegClass
{
private:
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I85598c078c604f1bebdba797308102482639c209
Gerrit-Change-Number: 49163
Gerrit-PatchSet: 37
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Bobby Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Daniel Carvalho <oda...@yahoo.com.br>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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