Attention is currently required from: Andreas Sandberg, Richard Cooper.
Hello Andreas Sandberg, Richard Cooper,
I'd like you to do a code review.
Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/56426
to review the following change.
Change subject: arch-arm: Replace MISCREG_CP14/15_UNIMPL with
MISCREG_UNKNOWN
......................................................................
arch-arm: Replace MISCREG_CP14/15_UNIMPL with MISCREG_UNKNOWN
MISCREG_UNKNOWN is the MiscRegIdx of an invalid AArch64 system
register. There is no need to define extra ids for AArch32 CP14/CP15
registers.
We are therefore removing them in favour of MISCREG_UNKNOWN instead
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Change-Id: Ib41813dfcb6a9cad84b7cef9603bc530cf4b593d
Reviewed-by: Richard Cooper <richard.coo...@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
---
M src/arch/arm/isa/formats/misc.isa
M src/arch/arm/regs/misc.cc
M src/arch/arm/regs/misc.hh
3 files changed, 25 insertions(+), 17 deletions(-)
diff --git a/src/arch/arm/isa/formats/misc.isa
b/src/arch/arm/isa/formats/misc.isa
index 32fccc8..0a11ba5 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -166,7 +166,7 @@
switch (miscReg) {
case MISCREG_NOP:
return new NopInst(machInst);
- case MISCREG_CP14_UNIMPL:
+ case MISCREG_UNKNOWN:
return new FailUnimplemented(isRead ? "mrc unknown" : "mcr
unknown",
machInst,
csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s
unknown",
@@ -211,7 +211,7 @@
case MISCREG_NOP:
return new McrMrcMiscInst(isRead ? "mrc nop" : "mcr nop",
machInst, iss, MISCREG_NOP);
- case MISCREG_CP15_UNIMPL:
+ case MISCREG_UNKNOWN:
return new FailUnimplemented(isRead ? "mrc unkown" : "mcr
unkown",
machInst,
csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s
unknown",
@@ -301,7 +301,7 @@
const bool isRead = bits(machInst, 20);
switch (miscReg) {
- case MISCREG_CP15_UNIMPL:
+ case MISCREG_UNKNOWN:
return new FailUnimplemented(isRead ? "mrc" : "mcr", machInst,
csprintf("miscreg crm:%d opc1:%d 64-bit %s unknown",
crm, opc1, isRead ? "read" : "write"));
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 0e58d93..0a95a55 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -333,7 +333,7 @@
// If we get here then it must be a register that we haven't
implemented
warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
crn, opc1, crm, opc2);
- return MISCREG_CP14_UNIMPL;
+ return MISCREG_UNKNOWN;
}
MiscRegIndex
@@ -1143,7 +1143,7 @@
return MISCREG_IMPDEF_UNIMPL;
}
// Unrecognized register
- return MISCREG_CP15_UNIMPL;
+ return MISCREG_UNKNOWN;
}
MiscRegIndex
@@ -1202,7 +1202,7 @@
break;
}
// Unrecognized register
- return MISCREG_CP15_UNIMPL;
+ return MISCREG_UNKNOWN;
}
std::tuple<bool, bool>
@@ -4545,12 +4545,6 @@
.allPrivileges();
InitReg(MISCREG_RAZ)
.allPrivileges().exceptUserMode().writes(0);
- InitReg(MISCREG_CP14_UNIMPL)
- .unimplemented()
- .warnNotFail();
- InitReg(MISCREG_CP15_UNIMPL)
- .unimplemented()
- .warnNotFail();
InitReg(MISCREG_UNKNOWN);
InitReg(MISCREG_IMPDEF_UNIMPL)
.unimplemented()
diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index ea58ad2..b70e3fe 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -1059,7 +1059,7 @@
// NUM_PHYS_MISCREGS specifies the number of actual physical
// registers, not considering the following pseudo-registers
- // (dummy registers), like UNKNOWN, CP15_UNIMPL,
MISCREG_IMPDEF_UNIMPL.
+ // (dummy registers), like MISCREG_UNKNOWN, MISCREG_IMPDEF_UNIMPL.
// Checkpointing should use this physical index when
// saving/restoring register values.
NUM_PHYS_MISCREGS,
@@ -1067,8 +1067,6 @@
// Dummy registers
MISCREG_NOP,
MISCREG_RAZ,
- MISCREG_CP14_UNIMPL,
- MISCREG_CP15_UNIMPL,
MISCREG_UNKNOWN,
// Implementation defined register: this represent
@@ -2206,8 +2204,6 @@
// Dummy registers
"nop",
"raz",
- "cp14_unimpl",
- "cp15_unimpl",
"unknown",
"impl_defined",
"erridr_el1",
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib41813dfcb6a9cad84b7cef9603bc530cf4b593d
Gerrit-Change-Number: 56426
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Richard Cooper <richard.coo...@arm.com>
Gerrit-Attention: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Attention: Richard Cooper <richard.coo...@arm.com>
Gerrit-MessageType: newchange
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