Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56449 )
Change subject: mem-ruby: Support partial DMA writes in MOESI_AMD_Base-dir
......................................................................
mem-ruby: Support partial DMA writes in MOESI_AMD_Base-dir
This stores the byte address for a DMA request in a TBE. When the
request is sent to memory, the byte address is passed as well. The
AbstractController handles the creation of a packet smaller than a
cacheline after this point.
Change-Id: Ie669906dcdbece5b2eb275adaf84237a067ef11c
---
M src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
1 file changed, 33 insertions(+), 16 deletions(-)
diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
b/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
index 41c09b1..b62854e 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
@@ -144,24 +144,25 @@
}
structure(TBE, desc="...") {
- State TBEState, desc="Transient state";
- DataBlock DataBlk, desc="data for the block";
- bool Dirty, desc="Is the data dirty?";
- int NumPendingAcks, desc="num acks expected";
- MachineID OriginalRequestor, desc="Original Requestor";
+ State TBEState, desc="Transient state";
+ DataBlock DataBlk, desc="data for the block";
+ bool Dirty, desc="Is the data dirty?";
+ int NumPendingAcks, desc="num acks expected";
+ MachineID OriginalRequestor, desc="Original Requestor";
MachineID WTRequestor, desc="WT Requestor";
- bool Cached, desc="data hit in Cache";
- bool MemData, desc="Got MemData?",default="false";
- bool wtData, desc="Got write through data?",default="false";
- bool atomicData, desc="Got Atomic op?",default="false";
- Cycles InitialRequestTime, desc="...";
- Cycles ForwardRequestTime, desc="...";
+ bool Cached, desc="data hit in Cache";
+ bool MemData, desc="Got MemData?", default="false";
+ bool wtData, desc="Got write through data?",
default="false";
+ bool atomicData, desc="Got Atomic op?", default="false";
+ Cycles InitialRequestTime, desc="...";
+ Cycles ForwardRequestTime, desc="...";
Cycles ProbeRequestStartTime, desc="...";
- MachineID LastSender, desc="Mach which this block came from";
- bool L3Hit, default="false", desc="Was this an L3 hit?";
- uint64_t probe_id, desc="probe id for lifetime profiling";
- WriteMask writeMask, desc="outstanding write through mask";
- int Len, desc="Length of memory request for DMA";
+ MachineID LastSender, desc="Mach which this block came from";
+ bool L3Hit, default="false", desc="Was this an L3 hit?";
+ uint64_t probe_id, desc="probe id for lifetime profiling";
+ WriteMask writeMask, desc="outstanding write through mask";
+ int Len, desc="Length of memory request for DMA";
+ Addr ByteAddr, default="0", desc="Byte address for DMA";
}
structure(TBETable, external="yes") {
@@ -893,6 +894,7 @@
tbe.NumPendingAcks := 0;
tbe.Dirty := false;
tbe.Len := in_msg.Len;
+ tbe.ByteAddr := in_msg.PhysicalAddress;
if (in_msg.Type == DMARequestType:WRITE) {
tbe.wtData := true;
tbe.Dirty := true;
@@ -950,6 +952,7 @@
out_msg.MessageSize := MessageSizeType:Writeback_Data;
out_msg.DataBlk := tbe.DataBlk;
out_msg.Len := tbe.Len;
+ out_msg.ByteAddr := tbe.ByteAddr;
DPRINTF(ProtocolTrace, "%s\n", out_msg);
}
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie669906dcdbece5b2eb275adaf84237a067ef11c
Gerrit-Change-Number: 56449
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-MessageType: newchange
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