Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/49107 )
(
38 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: cpu: Add generalized register accessors setReg and getReg.
......................................................................
cpu: Add generalized register accessors setReg and getReg.
These will read registers of any type, as described by a RegId. These
currently have default implementations which just delegate to the
existing, register type specific accessors.
Change-Id: I980ca15b3acd9a5a796c977276201d64c69398b8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49107
Maintainer: Giacomo Travaglini <[email protected]>
Reviewed-by: Giacomo Travaglini <[email protected]>
Maintainer: Gabe Black <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
2 files changed, 153 insertions(+), 0 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index 6203547..228f193 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -153,6 +153,127 @@
getSystemPtr()->threads.quiesceTick(contextId(), resume);
}
+RegVal
+ThreadContext::getReg(const RegId ®) const
+{
+ return getRegFlat(flattenRegId(reg));
+}
+
+void *
+ThreadContext::getWritableReg(const RegId ®)
+{
+ return getWritableRegFlat(flattenRegId(reg));
+}
+
+void
+ThreadContext::setReg(const RegId ®, RegVal val)
+{
+ setRegFlat(flattenRegId(reg), val);
+}
+
+void
+ThreadContext::getReg(const RegId ®, void *val) const
+{
+ getRegFlat(flattenRegId(reg), val);
+}
+
+void
+ThreadContext::setReg(const RegId ®, const void *val)
+{
+ setRegFlat(flattenRegId(reg), val);
+}
+
+RegVal
+ThreadContext::getRegFlat(const RegId ®) const
+{
+ RegVal val;
+ getRegFlat(reg, &val);
+ return val;
+}
+
+void
+ThreadContext::setRegFlat(const RegId ®, RegVal val)
+{
+ setRegFlat(reg, &val);
+}
+
+void
+ThreadContext::getRegFlat(const RegId ®, void *val) const
+{
+ const RegIndex idx = reg.index();
+ const RegClassType type = reg.classValue();
+ switch (type) {
+ case IntRegClass:
+ *(RegVal *)val = readIntRegFlat(idx);
+ break;
+ case FloatRegClass:
+ *(RegVal *)val = readFloatRegFlat(idx);
+ break;
+ case VecRegClass:
+ *(TheISA::VecRegContainer *)val = readVecRegFlat(idx);
+ break;
+ case VecElemClass:
+ *(RegVal *)val = readVecElemFlat(idx);
+ break;
+ case VecPredRegClass:
+ *(TheISA::VecPredRegContainer *)val = readVecPredRegFlat(idx);
+ break;
+ case CCRegClass:
+ *(RegVal *)val = readCCRegFlat(idx);
+ break;
+ case MiscRegClass:
+ panic("MiscRegs should not be read with getReg.");
+ default:
+ panic("Unrecognized register class type %d.", type);
+ }
+}
+
+void *
+ThreadContext::getWritableRegFlat(const RegId ®)
+{
+ const RegIndex idx = reg.index();
+ const RegClassType type = reg.classValue();
+ switch (type) {
+ case VecRegClass:
+ return &getWritableVecRegFlat(idx);
+ case VecPredRegClass:
+ return &getWritableVecPredRegFlat(idx);
+ default:
+ panic("Unrecognized register class type %d.", type);
+ }
+}
+
+void
+ThreadContext::setRegFlat(const RegId ®, const void *val)
+{
+ const RegIndex idx = reg.index();
+ const RegClassType type = reg.classValue();
+ switch (type) {
+ case IntRegClass:
+ setIntRegFlat(idx, *(RegVal *)val);
+ break;
+ case FloatRegClass:
+ setFloatRegFlat(idx, *(RegVal *)val);
+ break;
+ case VecRegClass:
+ setVecRegFlat(idx, *(TheISA::VecRegContainer *)val);
+ break;
+ case VecElemClass:
+ setVecElemFlat(idx, *(RegVal *)val);
+ break;
+ case VecPredRegClass:
+ setVecPredRegFlat(idx, *(TheISA::VecPredRegContainer *)val);
+ break;
+ case CCRegClass:
+ setCCRegFlat(idx, *(RegVal *)val);
+ break;
+ case MiscRegClass:
+ panic("MiscRegs should not be read with getReg.");
+ default:
+ panic("Unrecognized register class type %d.", type);
+ }
+}
+
void
serialize(const ThreadContext &tc, CheckpointOut &cp)
{
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index c1bae18..3d2d546 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -193,6 +193,13 @@
//
// New accessors for new decoder.
//
+ virtual RegVal getReg(const RegId ®) const;
+ virtual void getReg(const RegId ®, void *val) const;
+ virtual void *getWritableReg(const RegId ®);
+
+ virtual void setReg(const RegId ®, RegVal val);
+ virtual void setReg(const RegId ®, const void *val);
+
virtual RegVal readIntReg(RegIndex reg_idx) const = 0;
virtual RegVal readFloatReg(RegIndex reg_idx) const = 0;
@@ -272,6 +279,13 @@
* serialization code to access all registers.
*/
+ virtual RegVal getRegFlat(const RegId ®) const;
+ virtual void getRegFlat(const RegId ®, void *val) const;
+ virtual void *getWritableRegFlat(const RegId ®);
+
+ virtual void setRegFlat(const RegId ®, RegVal val);
+ virtual void setRegFlat(const RegId ®, const void *val);
+
virtual RegVal readIntRegFlat(RegIndex idx) const = 0;
virtual void setIntRegFlat(RegIndex idx, RegVal val) = 0;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I980ca15b3acd9a5a796c977276201d64c69398b8
Gerrit-Change-Number: 49107
Gerrit-PatchSet: 42
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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