Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56495 )
Change subject: arch-x86: Move spec, seq and debug microops to python.
......................................................................
arch-x86: Move spec, seq and debug microops to python.
These are the remaining, relatively simple types of microops, so lets
migrate them all at once.
Change-Id: Ie498f6e55d45c7c273fff0ca72291abc1170466b
---
M src/arch/x86/isa/microops/debug.isa
M src/arch/x86/isa/microops/seqop.isa
M src/arch/x86/isa/microops/specop.isa
M src/arch/x86/ucasmlib/arch/x86/microops/__init__.py
A src/arch/x86/ucasmlib/arch/x86/microops/debugop.py
A src/arch/x86/ucasmlib/arch/x86/microops/seqop.py
A src/arch/x86/ucasmlib/arch/x86/microops/specop.py
7 files changed, 303 insertions(+), 191 deletions(-)
diff --git a/src/arch/x86/isa/microops/debug.isa
b/src/arch/x86/isa/microops/debug.isa
index 62c313f..d9672fc 100644
--- a/src/arch/x86/isa/microops/debug.isa
+++ b/src/arch/x86/isa/microops/debug.isa
@@ -94,67 +94,3 @@
exec_output = MicroDebugFlagsExecute.subst(iop)
decoder_output = MicroDebugFlagsConstructor.subst(iop)
}};
-
-let {{
- class MicroDebug(X86Microop):
- def __init__(self, name, fault, message, once, flags):
- self.name = name
- self.fault = fault
- self.message = message
- self.once = once
- self.flags = flags
- if flags and not isinstance(flags, (list, tuple)):
- raise Exception("flags must be a list or tuple of flags")
-
- self.className = "MicroDebugFlags" if flags else "MicroDebug"
-
- def getAllocator(self, microFlags):
- if self.once:
- fault_allocator_template = \
- "new %(fault_type)s(%(token)s, %(message)s)"
- else:
- fault_allocator_template = \
- "new %(fault_type)s(%(message)s)"
- fault_allocator = fault_allocator_template % {
- "fault_type": self.fault,
- "token": "std::string(\"%s\")" % self.message,
- "message": "\"%s\"" % self.message
- }
-
- args = ["machInst", "\"%s\"" % self.name, "macrocodeBlock",
- self.microFlagsText(microFlags), fault_allocator]
-
- if self.flags:
- args.append(" | ".join(self.flags))
-
- return "new " + self.className + "(" + ", ".join(args) + ")"
-
- def buildDebugMicro(name, with_once=False):
- global microopClasses
-
- fault_class = "GenericISA::M5" + name.capitalize() + "Fault"
-
- class MicroDebugChild(MicroDebug):
- def __init__(self, message, flags=None):
- super().__init__(name, fault_class, message, False, flags)
-
- microopClasses[name] = MicroDebugChild
-
- if with_once:
- fault_once_class = \
- "GenericISA::M5" + name.capitalize() + "OnceFault"
- name_once = name + "_once"
-
- class MicroDebugOnceChild(MicroDebug):
- def __init__(self, message, flags=None):
- super().__init__(
- name_once, fault_once_class, message, True,
flags)
-
- microopClasses[name_once] = MicroDebugOnceChild
-
- buildDebugMicro("panic")
- buildDebugMicro("fatal")
- buildDebugMicro("hack", True)
- buildDebugMicro("inform", True)
- buildDebugMicro("warn", True)
-}};
diff --git a/src/arch/x86/isa/microops/seqop.isa
b/src/arch/x86/isa/microops/seqop.isa
index 1c8ce63..3720a3e 100644
--- a/src/arch/x86/isa/microops/seqop.isa
+++ b/src/arch/x86/isa/microops/seqop.isa
@@ -106,72 +106,22 @@
}};
let {{
- class Br(X86Microop):
- def __init__(self, target, flags=None):
- self.className = "Br"
- self.target = target
- if flags:
- if not isinstance(flags, (list, tuple)):
- raise Exception("flags must be a list or tuple of
flags")
- self.cond = " | ".join(flags)
- self.className += "Flags"
- else:
- self.cond = "0"
-
- def getAllocator(self, microFlags):
- if "IsLastMicroop" in microFlags:
- microFlags.remove("IsLastMicroop")
- if not "IsDelayedCommit" in microFlags:
- microFlags.append("IsDelayedCommit")
-
- return '''new %(class_name)s(machInst, macrocodeBlock,
- %(flags)s, %(target)s, %(cc)s)''' % {
- "class_name" : self.className,
- "flags" : self.microFlagsText(microFlags),
- "target" : self.target,
- "cc" : self.cond}
- microopClasses["br"] = Br
-
- class Eret(X86Microop):
- def __init__(self, flags=None):
- self.className = "Eret"
- if flags:
- if not isinstance(flags, (list, tuple)):
- raise Exception("flags must be a list or tuple of
flags")
- self.cond = " | ".join(flags)
- self.className += "Flags"
- else:
- self.cond = "X86ISA::condition_tests::True"
-
- def getAllocator(self, microFlags):
- if not "IsLastMicroop" in microFlags:
- microFlags.append("IsLastMicroop")
- if "IsDelayedCommit" in microFlags:
- microFlags.remove("IsDelayedCommit")
-
- return '''new %(class_name)s(machInst, macrocodeBlock,
- %(flags)s, %(cc)s)''' % {
- "class_name" : self.className,
- "flags" : self.microFlagsText(microFlags),
- "cc" : self.cond}
- microopClasses["eret"] = Eret
-
- cond_code = "checkCondition(ccFlagBits | cfofBits | dfBit |" \
- "ecfBit | ezfBit, cc)"
+ cond_code = 'checkCondition(ccFlagBits | cfofBits | dfBit |' \
+ 'ecfBit | ezfBit, cc)'
for suffix, cond, flags in \
- ("Flags", cond_code, ["IsDirectControl", "IsCondControl"]), \
- ("", "true", []):
- iop = InstObjParams("br", "Br" + suffix,
- "X86ISA::InstOperands<X86ISA::MicroCondBase,
X86ISA::UpcOp>",
- {"code": "nuIP = target;", "else_code": "nuIP = nuIP;",
- "cond_test": cond},
+ ('Flags', cond_code, ['IsDirectControl', 'IsCondControl']), \
+ ('', 'true', []):
+ iop = InstObjParams('br', 'Br' + suffix,
+ 'X86ISA::InstOperands<X86ISA::MicroCondBase,
X86ISA::UpcOp>',
+ {'code': 'nuIP = target;', 'else_code': 'nuIP = nuIP;',
+ 'cond_test': cond},
flags)
exec_output += SeqOpExecute.subst(iop)
header_output += BrDeclare.subst(iop)
- iop = InstObjParams("eret", "Eret" + suffix,
- "X86ISA::InstOperands<X86ISA::MicroCondBase>",
- {"code": "", "else_code": "", "cond_test": cond}, flags)
+ iop = InstObjParams('eret', 'Eret' + suffix,
+ 'X86ISA::InstOperands<X86ISA::MicroCondBase>',
+ {'code': '', 'else_code': '', 'cond_test': cond}, flags)
exec_output += SeqOpExecute.subst(iop)
header_output += EretDeclare.subst(iop)
}};
diff --git a/src/arch/x86/isa/microops/specop.isa
b/src/arch/x86/isa/microops/specop.isa
index 0a720ee..a55628d 100644
--- a/src/arch/x86/isa/microops/specop.isa
+++ b/src/arch/x86/isa/microops/specop.isa
@@ -83,54 +83,21 @@
}};
let {{
- class Fault(X86Microop):
- className = "MicroFault"
- def __init__(self, fault, flags=None):
- self.fault = fault
- if flags:
- if not isinstance(flags, (list, tuple)):
- raise Exception("flags must be a list or tuple of
flags")
- self.cond = " | ".join(flags)
- self.className += "Flags"
- else:
- self.cond = "0"
-
- def getAllocator(self, microFlags):
- allocator = '''new %(class_name)s(machInst, macrocodeBlock,
- %(flags)s, %(fault)s, %(cc)s)''' % {
- "class_name" : self.className,
- "flags" : self.microFlagsText(microFlags),
- "fault" : self.fault,
- "cc" : self.cond}
- return allocator
-
- iop = InstObjParams("fault", "MicroFaultFlags",
- "X86ISA::InstOperands<X86ISA::MicroCondBase, X86ISA::FaultOp>",
- {"code": "",
- "cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \
- ecfBit | ezfBit, cc)"})
+ iop = InstObjParams('fault', 'MicroFaultFlags',
+ 'X86ISA::InstOperands<X86ISA::MicroCondBase, X86ISA::FaultOp>',
+ {'code': '',
+ 'cond_test': 'checkCondition(ccFlagBits | cfofBits | dfBit
| ' \
+ 'ecfBit | ezfBit, cc)'})
exec_output = MicroFaultExecute.subst(iop)
header_output = MicroFaultDeclare.subst(iop)
decoder_output = MicroFaultConstructor.subst(iop)
- iop = InstObjParams("fault", "MicroFault",
- "X86ISA::InstOperands<X86ISA::MicroCondBase, X86ISA::FaultOp>",
- {"code": "",
- "cond_test": "true"})
+
+ iop = InstObjParams('fault', 'MicroFault',
+ 'X86ISA::InstOperands<X86ISA::MicroCondBase, X86ISA::FaultOp>',
+ {'code': '', 'cond_test': 'true'})
exec_output += MicroFaultExecute.subst(iop)
header_output += MicroFaultDeclare.subst(iop)
decoder_output += MicroFaultConstructor.subst(iop)
- microopClasses["fault"] = Fault
-
- class Halt(X86Microop):
- className = "MicroHalt"
- def __init__(self):
- pass
-
- def getAllocator(self, microFlags):
- return "new X86ISA::MicroHalt(machInst, macrocodeBlock, %s)" %
\
- self.microFlagsText(microFlags)
-
- microopClasses["halt"] = Halt
}};
def template MicroFenceOpDeclare {{
@@ -163,31 +130,8 @@
}};
let {{
- class MfenceOp(X86Microop):
- def __init__(self):
- self.className = "Mfence"
- self.mnemonic = "mfence"
- self.instFlags = "| (1ULL << StaticInst::IsReadBarrier)" + \
- "| (1ULL << StaticInst::IsWriteBarrier)"
-
- def getAllocator(self, microFlags):
- allocString = '''
- (StaticInstPtr)(new %(class_name)s(machInst,
- macrocodeBlock, %(flags)s))
- '''
- allocator = allocString % {
- "class_name" : self.className,
- "mnemonic" : self.mnemonic,
- "flags" : self.microFlagsText(microFlags) + self.instFlags}
- return allocator
-
- microopClasses["mfence"] = MfenceOp
-}};
-
-let {{
# Build up the all register version of this micro op
- iop = InstObjParams("mfence", "Mfence", 'X86MicroopBase',
- {"code" : ""})
+ iop = InstObjParams('mfence', 'Mfence', 'X86MicroopBase',
{'code' : ''})
header_output += MicroFenceOpDeclare.subst(iop)
decoder_output += MicroFenceOpConstructor.subst(iop)
}};
diff --git a/src/arch/x86/ucasmlib/arch/x86/microops/__init__.py
b/src/arch/x86/ucasmlib/arch/x86/microops/__init__.py
index 418c8be..f6b2a3a 100644
--- a/src/arch/x86/ucasmlib/arch/x86/microops/__init__.py
+++ b/src/arch/x86/ucasmlib/arch/x86/microops/__init__.py
@@ -63,3 +63,15 @@
from . import mediaop
microops.update(mediaop.microops)
microops.mediaops = mediaop.mediaops
+
+# Add the sequencing microops.
+from . import seqop
+microops.update(seqop.microops)
+
+# Add the special microops.
+from . import specop
+microops.update(specop.microops)
+
+# Add the debug microops.
+from . import debugop
+microops.update(debugop.microops)
diff --git a/src/arch/x86/ucasmlib/arch/x86/microops/debugop.py
b/src/arch/x86/ucasmlib/arch/x86/microops/debugop.py
new file mode 100644
index 0000000..ae8817a
--- /dev/null
+++ b/src/arch/x86/ucasmlib/arch/x86/microops/debugop.py
@@ -0,0 +1,93 @@
+# Copyright 2008 The Hewlett-Packard Development Company
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from .base import X86Microop
+
+microops = {}
+
+class MicroDebug(X86Microop):
+ def __init__(self, name, fault, message, once, flags):
+ self.name = name
+ self.fault = fault
+ self.message = message
+ self.once = once
+ self.flags = flags
+ if flags and not isinstance(flags, (list, tuple)):
+ raise Exception('flags must be a list or tuple of flags')
+
+ self.className = 'MicroDebugFlags' if flags else 'MicroDebug'
+
+ def getAllocator(self, microFlags):
+ if self.once:
+ fault_allocator = f'new {self.fault}(' \
+ f'std::string("{self.message}"), "{self.message}")'
+ else:
+ fault_allocator = f'new {self.fault}("{self.message}")'
+
+ args = ['machInst', f'"{self.name}"', 'macrocodeBlock',
+ self.microFlagsText(microFlags), fault_allocator]
+
+ if self.flags:
+ args.append(' | '.join(self.flags))
+
+ return f'new {self.className}({", ".join(args)})'
+
+def buildDebugMicro(name, with_once=False):
+ global microops
+
+ fault_class = f'GenericISA::M5{name.capitalize()}Fault'
+
+ class MicroDebugChild(MicroDebug):
+ def __init__(self, message, flags=None):
+ super().__init__(name, fault_class, message, False, flags)
+
+ microops[name] = MicroDebugChild
+
+ if not with_once:
+ return
+
+ fault_once_class = f'GenericISA::M5{name.capitalize()}OnceFault'
+ name_once = f'{name}_once'
+
+ class MicroDebugOnceChild(MicroDebug):
+ def __init__(self, message, flags=None):
+ super().__init__(name_once, fault_once_class, message, True,
flags)
+
+ microops[name_once] = MicroDebugOnceChild
+
+buildDebugMicro('panic')
+buildDebugMicro('fatal')
+buildDebugMicro('hack', True)
+buildDebugMicro('inform', True)
+buildDebugMicro('warn', True)
diff --git a/src/arch/x86/ucasmlib/arch/x86/microops/seqop.py
b/src/arch/x86/ucasmlib/arch/x86/microops/seqop.py
new file mode 100644
index 0000000..35e076c
--- /dev/null
+++ b/src/arch/x86/ucasmlib/arch/x86/microops/seqop.py
@@ -0,0 +1,83 @@
+# Copyright 2008 The Hewlett-Packard Development Company
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from .base import X86Microop
+
+microops = {}
+
+class Br(X86Microop):
+ def __init__(self, target, flags=None):
+ self.className = 'Br'
+ self.target = target
+ if flags:
+ if not isinstance(flags, (list, tuple)):
+ raise Exception('flags must be a list or tuple of flags')
+ self.cond = ' | '.join(flags)
+ self.className += 'Flags'
+ else:
+ self.cond = '0'
+
+ def getAllocator(self, microFlags):
+ if 'IsLastMicroop' in microFlags:
+ microFlags.remove('IsLastMicroop')
+ if not 'IsDelayedCommit' in microFlags:
+ microFlags.append('IsDelayedCommit')
+
+ return f'''new {self.className}(machInst, macrocodeBlock,
+ {self.microFlagsText(microFlags)}, {self.target},
+ {self.cond})'''
+
+microops['br'] = Br
+
+class Eret(X86Microop):
+ def __init__(self, flags=None):
+ self.className = 'Eret'
+ if flags:
+ if not isinstance(flags, (list, tuple)):
+ raise Exception('flags must be a list or tuple of flags')
+ self.cond = ' | '.join(flags)
+ self.className += 'Flags'
+ else:
+ self.cond = 'X86ISA::condition_tests::True'
+
+ def getAllocator(self, microFlags):
+ if not 'IsLastMicroop' in microFlags:
+ microFlags.append('IsLastMicroop')
+ if 'IsDelayedCommit' in microFlags:
+ microFlags.remove('IsDelayedCommit')
+
+ return f'''new {self.className}(machInst, macrocodeBlock,
+ {self.microFlagsText(microFlags)}, {self.cond})'''
+
+microops['eret'] = Eret
diff --git a/src/arch/x86/ucasmlib/arch/x86/microops/specop.py
b/src/arch/x86/ucasmlib/arch/x86/microops/specop.py
new file mode 100644
index 0000000..fa5066f
--- /dev/null
+++ b/src/arch/x86/ucasmlib/arch/x86/microops/specop.py
@@ -0,0 +1,82 @@
+# Copyright 2007-2008 The Hewlett-Packard Development Company
+# Copyright 2011 Mark D. Hill and David A. Wood
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from .base import X86Microop
+
+microops = {}
+
+class Fault(X86Microop):
+ className = 'MicroFault'
+ def __init__(self, fault, flags=None):
+ self.fault = fault
+ if flags:
+ if not isinstance(flags, (list, tuple)):
+ raise Exception('flags must be a list or tuple of flags')
+ self.cond = ' | '.join(flags)
+ self.className += 'Flags'
+ else:
+ self.cond = '0'
+
+ def getAllocator(self, microFlags):
+ allocator = f'''new {self.className}(machInst, macrocodeBlock,
+ {self.microFlagsText(microFlags)}, {self.fault},
+ {self.cond})'''
+ return allocator
+
+microops['fault'] = Fault
+
+class Halt(X86Microop):
+ className = 'MicroHalt'
+ def __init__(self):
+ pass
+
+ def getAllocator(self, microFlags):
+ return 'new X86ISA::MicroHalt(machInst, macrocodeBlock, ' \
+ f'{self.microFlagsText(microFlags)})'
+
+microops['halt'] = Halt
+
+class MfenceOp(X86Microop):
+ def __init__(self):
+ self.className = 'Mfence'
+ self.mnemonic = 'mfence'
+ self.instFlags = '| (1ULL << StaticInst::IsReadBarrier)' \
+ '| (1ULL << StaticInst::IsWriteBarrier)'
+
+ def getAllocator(self, microFlags):
+ return f'new {self.className}(machInst, macrocodeBlock, ' \
+ f'{self.microFlagsText(microFlags) + self.instFlags})'
+
+microops['mfence'] = MfenceOp
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie498f6e55d45c7c273fff0ca72291abc1170466b
Gerrit-Change-Number: 56495
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
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