Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56600 )
Change subject: cpu: Allow TLB shootdown requests in the o3 cpu
......................................................................
cpu: Allow TLB shootdown requests in the o3 cpu
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
Change-Id: Ie698efd583f592e5564af01c2150fbec969f56a2
---
M src/cpu/o3/lsq.cc
M src/cpu/o3/lsq.hh
2 files changed, 34 insertions(+), 14 deletions(-)
diff --git a/src/cpu/o3/lsq.cc b/src/cpu/o3/lsq.cc
index c932a93..375093a 100644
--- a/src/cpu/o3/lsq.cc
+++ b/src/cpu/o3/lsq.cc
@@ -784,15 +784,16 @@
assert(!isAtomic || (isAtomic && !needs_burst));
const bool htm_cmd = isLoad && (flags & Request::HTM_CMD);
+ const bool tlbi_cmd = isLoad && (flags & Request::TLBI_CMD);
if (inst->translationStarted()) {
request = inst->savedRequest;
assert(request);
} else {
- if (htm_cmd) {
+ if (htm_cmd || tlbi_cmd) {
assert(addr == 0x0lu);
assert(size == 8);
- request = new HtmCmdRequest(&thread[tid], inst, flags);
+ request = new UnsquashableDirectRequest(&thread[tid], inst,
flags);
} else if (needs_burst) {
request = new SplitDataRequest(&thread[tid], inst, isLoad,
addr,
size, flags, data, res);
@@ -1377,15 +1378,17 @@
lsq->recvReqRetry();
}
-LSQ::HtmCmdRequest::HtmCmdRequest(LSQUnit* port, const DynInstPtr& inst,
- const Request::Flags& flags_) :
+LSQ::UnsquashableDirectRequest::UnsquashableDirectRequest(
+ LSQUnit* port,
+ const DynInstPtr& inst,
+ const Request::Flags& flags_) :
SingleDataRequest(port, inst, true, 0x0lu, 8, flags_,
nullptr, nullptr, nullptr)
{
}
void
-LSQ::HtmCmdRequest::initiateTranslation()
+LSQ::UnsquashableDirectRequest::initiateTranslation()
{
// Special commands are implemented as loads to avoid significant
// changes to the cpu and memory interfaces
@@ -1421,8 +1424,9 @@
}
void
-LSQ::HtmCmdRequest::finish(const Fault &fault, const RequestPtr &req,
- gem5::ThreadContext* tc, BaseMMU::Mode mode)
+LSQ::UnsquashableDirectRequest::finish(const Fault &fault,
+ const RequestPtr &req, gem5::ThreadContext* tc,
+ BaseMMU::Mode mode)
{
panic("unexpected behaviour - finish()");
}
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 2e99455..1d4ecfd 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -583,19 +583,24 @@
virtual std::string name() const { return "SingleDataRequest"; }
};
- // hardware transactional memory
- // This class extends SingleDataRequest for the sole purpose
- // of encapsulating hardware transactional memory command requests
- class HtmCmdRequest : public SingleDataRequest
+ // This class extends SingleDataRequest for the purpose
+ // of allowing special requests (eg Hardware transactional memory, TLB
+ // shootdowns) to bypass irrelevant system elements like translation &
+ // squashing.
+ class UnsquashableDirectRequest : public SingleDataRequest
{
public:
- HtmCmdRequest(LSQUnit* port, const DynInstPtr& inst,
+ UnsquashableDirectRequest(LSQUnit* port, const DynInstPtr& inst,
const Request::Flags& flags_);
- virtual ~HtmCmdRequest() {}
+ inline virtual ~UnsquashableDirectRequest() {}
virtual void initiateTranslation();
virtual void finish(const Fault &fault, const RequestPtr &req,
gem5::ThreadContext* tc, BaseMMU::Mode mode);
- virtual std::string name() const { return "HtmCmdRequest"; }
+ virtual std::string
+ name() const
+ {
+ return "UnsquashableDirectRequest";
+ }
};
class SplitDataRequest : public LSQRequest
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie698efd583f592e5564af01c2150fbec969f56a2
Gerrit-Change-Number: 56600
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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