Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56604 )
Change subject: arch-arm: Add DVM ISA templates
......................................................................
arch-arm: Add DVM ISA templates
These will be used by DVM instructions:
* TLBI Shareable
* DSB Shareable
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
Change-Id: I32f83e08360ceb7ba324d07c72fe6addeb4bbbca
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/isa/templates/misc64.isa
1 file changed, 112 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/isa/templates/misc64.isa
b/src/arch/arm/isa/templates/misc64.isa
index faad349..7a10463 100644
--- a/src/arch/arm/isa/templates/misc64.isa
+++ b/src/arch/arm/isa/templates/misc64.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2011,2017-2020 ARM Limited
+// Copyright (c) 2011,2017-2021 Arm Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -161,6 +161,24 @@
}
}};
+def template MiscRegRegMemOp64Declare {{
+class %(class_name)s : public %(base_class)s
+{
+ private:
+ %(reg_idx_arr_decl)s;
+
+ public:
+ // Constructor
+ %(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
+ IntRegIndex _op1, uint64_t _imm);
+
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault completeAcc(PacketPtr, ExecContext *,
+ Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, Trace::InstRecord *) const override;
+};
+}};
+
def template RegMiscRegOp64Declare {{
class %(class_name)s : public %(base_class)s
{
@@ -233,3 +251,79 @@
%(constructor)s;
}
}};
+
+def template DvmDeclare {{
+ /**
+ * Static instruction class for "%(mnemonic)s".
+ */
+ class %(class_name)s : public %(base_class)s
+ {
+ private:
+ %(reg_idx_arr_decl)s;
+
+ public:
+ /// Constructor.
+ %(class_name)s(ExtMachInst machInst);
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const
override;
+ Fault completeAcc(PacketPtr, ExecContext *,
+ Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ };
+}};
+
+def template DvmTlbiConstructor {{
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, MiscRegIndex
_dest,
+ IntRegIndex _op1, uint64_t _imm) :
+ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+ _dest, _op1, _imm)
+ {
+ %(set_reg_idx_arr)s;
+ %(constructor)s;
+
+ if (machInst.dvmEnabled) {
+ flags[IsLoad] = true;
+ }
+ }
+}};
+
+def template DvmConstructor {{
+ %(class_name)s::%(class_name)s(ExtMachInst machInst) :
+ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+ {
+ %(set_reg_idx_arr)s;
+ %(constructor)s;
+
+ if (machInst.dvmEnabled) {
+ flags[IsLoad] = true;
+ }
+ }
+}};
+
+def template DvmInitiateAcc {{
+ Fault
+ %(class_name)s::initiateAcc(ExecContext *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+
+ %(op_decl)s;
+ %(op_rd)s;
+ %(code)s;
+
+ %(dvm_code)s;
+
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+ return fault;
+ }
+}};
+
+def template DvmCompleteAcc {{
+ Fault
+ %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
+ Trace::InstRecord *traceData) const
+ {
+ return NoFault;
+ }
+}};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I32f83e08360ceb7ba324d07c72fe6addeb4bbbca
Gerrit-Change-Number: 56604
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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