Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/56603 )

Change subject: arch-arm: Add DVM enabled flag in the ExtMachInst/Decoder class
......................................................................

arch-arm: Add DVM enabled flag in the ExtMachInst/Decoder class

This is needed as the decoder needs to choose whether to
instantiate a DVM (treated as IsLoad) instruction when
decoding a TLBI/DSB Shareable, or to issue a simple system
instruction in case DVM messages are not modelled in the
simulated system.

JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I9f46304dee63851caec809a5c6b8e796d684cc05
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/ArmDecoder.py
M src/arch/arm/decoder.cc
M src/arch/arm/decoder.hh
M src/arch/arm/types.hh
4 files changed, 43 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/ArmDecoder.py b/src/arch/arm/ArmDecoder.py
index 9f01af6..a5c16f5 100644
--- a/src/arch/arm/ArmDecoder.py
+++ b/src/arch/arm/ArmDecoder.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2021 Arm Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright 2021 Google, Inc.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -23,9 +35,13 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+from m5.params import *
 from m5.objects.InstDecoder import InstDecoder

 class ArmDecoder(InstDecoder):
     type = 'ArmDecoder'
     cxx_class = 'gem5::ArmISA::Decoder'
     cxx_header = "arch/arm/decoder.hh"
+
+    dvm_enabled = Param.Bool(False,
+        "Does the decoder implement DVM operations")
diff --git a/src/arch/arm/decoder.cc b/src/arch/arm/decoder.cc
index 9d90537..48a8641 100644
--- a/src/arch/arm/decoder.cc
+++ b/src/arch/arm/decoder.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2014,2018 ARM Limited
+ * Copyright (c) 2012-2014,2018, 2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -56,6 +56,7 @@

 Decoder::Decoder(const ArmDecoderParams &params)
     : InstDecoder(params, &data), data(0), fpscrLen(0), fpscrStride(0),
+      dvmEnabled(params.dvm_enabled),
       decoderFlavor(dynamic_cast<ISA *>(params.isa)->decoderFlavor())
 {
     reset();
@@ -188,6 +189,7 @@
     this_emi.itstate = pc.itstate();
     this_emi.illegalExecution = pc.illegalExec() ? 1 : 0;
     this_emi.debugStep = pc.debugStep() ? 1 : 0;
+    this_emi.dvmEnabled = dvmEnabled;
     pc.size(inst_size);

     emi = 0;
diff --git a/src/arch/arm/decoder.hh b/src/arch/arm/decoder.hh
index 62d6f54..e1d2bed 100644
--- a/src/arch/arm/decoder.hh
+++ b/src/arch/arm/decoder.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014 ARM Limited
+ * Copyright (c) 2013-2014, 2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -80,6 +80,9 @@
      */
     int sveLen;

+    /** True if the decoder should emit DVM Ops (treated as Loads( */
+    const bool dvmEnabled;
+
     enums::DecoderFlavor decoderFlavor;

     /// A cache of decoded instruction objects.
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 734fe6f..9693fc3 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -71,6 +71,8 @@
         Bitfield<55, 52> itstateCond;
         Bitfield<51, 48> itstateMask;

+        Bitfield<42>     dvmEnabled;
+
         // FPSCR fields
         Bitfield<41, 40> fpscrStride;
         Bitfield<39, 37> fpscrLen;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9f46304dee63851caec809a5c6b8e796d684cc05
Gerrit-Change-Number: 56603
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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