Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56601 )
Change subject: arch-arm: Add helper MISCREG to track a pending DVM
operation
......................................................................
arch-arm: Add helper MISCREG to track a pending DVM operation
We are introducing the MISCREG_TLBINEEDSYNC misc register to track
the presence of a pending DVM (TLBI) operation.
It will be used by:
* TLBI instructions: setting up the flag to indicate there
is a pending DVM message
* DSB instruction: clearing the flag indicating the DVM
messgage has been syncronized
Change-Id: I7a599ada5a6ac6f86ed2260caa872f085c889ab5
---
M src/arch/arm/regs/misc.cc
M src/arch/arm/regs/misc.hh
2 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 0e58d93..109d0fb 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2079,6 +2079,8 @@
.allPrivileges();
InitReg(MISCREG_SEV_MAILBOX)
.allPrivileges();
+ InitReg(MISCREG_TLBINEEDSYNC)
+ .allPrivileges().exceptUserMode();
// AArch32 CP14 registers
InitReg(MISCREG_DBGDIDR)
diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index ea58ad2..479d02e 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -90,6 +90,7 @@
MISCREG_PMXEVTYPER_PMCCFILTR,
MISCREG_SCTLR_RST,
MISCREG_SEV_MAILBOX,
+ MISCREG_TLBINEEDSYNC,
// AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
MISCREG_DBGDIDR,
@@ -1245,6 +1246,7 @@
"pmxevtyper_pmccfiltr",
"sctlr_rst",
"sev_mailbox",
+ "tlbi_needsync",
// AArch32 CP14 registers
"dbgdidr",
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7a599ada5a6ac6f86ed2260caa872f085c889ab5
Gerrit-Change-Number: 56601
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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