Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/49693 )
Change subject: cpu: In SimpleExecContext, use arrays to map reg classes to
stats.
......................................................................
cpu: In SimpleExecContext, use arrays to map reg classes to stats.
Use arrays to more efficiently look up what stats to increment instead
of using switch statements.
Change-Id: I845d0c01ba5b930d46b36147a3136fd721241ed9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49693
Reviewed-by: Giacomo Travaglini <[email protected]>
Maintainer: Giacomo Travaglini <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/cpu/simple/exec_context.hh
1 file changed, 41 insertions(+), 88 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 34dc2d6..98adf36 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -157,7 +157,23 @@
ADD_STAT(numBranchMispred, statistics::units::Count::get(),
"Number of branch mispredictions"),
ADD_STAT(statExecutedInstType,
statistics::units::Count::get(),
- "Class of executed instruction.")
+ "Class of executed instruction."),
+ numRegReads{
+ &numIntRegReads,
+ &numFpRegReads,
+ &numVecRegReads,
+ &numVecRegReads,
+ &numVecPredRegReads,
+ &numCCRegReads
+ },
+ numRegWrites{
+ &numIntRegWrites,
+ &numFpRegWrites,
+ &numVecRegWrites,
+ &numVecRegWrites,
+ &numVecPredRegWrites,
+ &numCCRegWrites
+ }
{
numCCRegReads
.flags(statistics::nozero);
@@ -278,6 +294,9 @@
// Instruction mix histogram by OpClass
statistics::Vector statExecutedInstType;
+ std::array<statistics::Scalar *, CCRegClass + 1> numRegReads;
+ std::array<statistics::Scalar *, CCRegClass + 1> numRegWrites;
+
} execContextStats;
public:
@@ -292,23 +311,7 @@
getRegOperand(const StaticInst *si, int idx) override
{
const RegId ® = si->srcRegIdx(idx);
- const RegClassType type = reg.classValue();
- switch (type) {
- case IntRegClass:
- execContextStats.numIntRegReads++;
- break;
- case FloatRegClass:
- execContextStats.numFpRegReads++;
- break;
- case CCRegClass:
- execContextStats.numCCRegReads++;
- break;
- case VecElemClass:
- execContextStats.numVecRegReads++;
- break;
- default:
- break;
- }
+ (*execContextStats.numRegReads[reg.classValue()])++;
return thread->getReg(reg);
}
@@ -316,27 +319,7 @@
getRegOperand(const StaticInst *si, int idx, void *val) override
{
const RegId ® = si->srcRegIdx(idx);
- const RegClassType type = reg.classValue();
- switch (type) {
- case IntRegClass:
- execContextStats.numIntRegReads++;
- break;
- case FloatRegClass:
- execContextStats.numFpRegReads++;
- break;
- case VecRegClass:
- case VecElemClass:
- execContextStats.numVecRegReads++;
- break;
- case VecPredRegClass:
- execContextStats.numVecPredRegReads++;
- break;
- case CCRegClass:
- execContextStats.numCCRegReads++;
- break;
- default:
- break;
- }
+ (*execContextStats.numRegReads[reg.classValue()])++;
thread->getReg(reg, val);
}
@@ -344,17 +327,7 @@
getWritableRegOperand(const StaticInst *si, int idx) override
{
const RegId ® = si->destRegIdx(idx);
- const RegClassType type = reg.classValue();
- switch (type) {
- case VecRegClass:
- execContextStats.numVecRegWrites++;
- break;
- case VecPredRegClass:
- execContextStats.numVecPredRegWrites++;
- break;
- default:
- break;
- }
+ (*execContextStats.numRegWrites[reg.classValue()])++;
return thread->getWritableReg(reg);
}
@@ -362,23 +335,7 @@
setRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId ® = si->destRegIdx(idx);
- const RegClassType type = reg.classValue();
- switch (type) {
- case IntRegClass:
- execContextStats.numIntRegWrites++;
- break;
- case FloatRegClass:
- execContextStats.numFpRegWrites++;
- break;
- case CCRegClass:
- execContextStats.numCCRegWrites++;
- break;
- case VecElemClass:
- execContextStats.numVecRegWrites++;
- break;
- default:
- break;
- }
+ (*execContextStats.numRegWrites[reg.classValue()])++;
thread->setReg(reg, val);
}
@@ -386,27 +343,7 @@
setRegOperand(const StaticInst *si, int idx, const void *val) override
{
const RegId ® = si->destRegIdx(idx);
- const RegClassType type = reg.classValue();
- switch (type) {
- case IntRegClass:
- execContextStats.numIntRegWrites++;
- break;
- case FloatRegClass:
- execContextStats.numFpRegWrites++;
- break;
- case VecRegClass:
- case VecElemClass:
- execContextStats.numVecRegWrites++;
- break;
- case VecPredRegClass:
- execContextStats.numVecPredRegWrites++;
- break;
- case CCRegClass:
- execContextStats.numCCRegWrites++;
- break;
- default:
- break;
- }
+ (*execContextStats.numRegWrites[reg.classValue()])++;
thread->setReg(reg, val);
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I845d0c01ba5b930d46b36147a3136fd721241ed9
Gerrit-Change-Number: 49693
Gerrit-PatchSet: 50
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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