[gem5-dev] Change in gem5/gem5[develop]: cpu: Remove the default implementation of (get|set)RegFlat.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49698 )

 (
50 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: cpu: Remove the default implementation of (get| 
set)RegFlat.
......................................................................

cpu: Remove the default implementation of (get|set)RegFlat.

This was originally intended to call back into the original readIntReg,
setIntReg, etc, but now that *those* are implemented by calling into
getRegFlat, setRegFlat, etc, that's a circular dependency and makes that
implementation unusable.

Change-Id: I4135f0d8721f5f9d724be590767bed0023a9de20
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49698
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
2 files changed, 21 insertions(+), 80 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index 228f193..181c583 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -198,83 +198,6 @@
 }

 void
-ThreadContext::getRegFlat(const RegId &reg, void *val) const
-{
-    const RegIndex idx = reg.index();
-    const RegClassType type = reg.classValue();
-    switch (type) {
-      case IntRegClass:
-        *(RegVal *)val = readIntRegFlat(idx);
-        break;
-      case FloatRegClass:
-        *(RegVal *)val = readFloatRegFlat(idx);
-        break;
-      case VecRegClass:
-        *(TheISA::VecRegContainer *)val = readVecRegFlat(idx);
-        break;
-      case VecElemClass:
-        *(RegVal *)val = readVecElemFlat(idx);
-        break;
-      case VecPredRegClass:
-        *(TheISA::VecPredRegContainer *)val = readVecPredRegFlat(idx);
-        break;
-      case CCRegClass:
-        *(RegVal *)val = readCCRegFlat(idx);
-        break;
-      case MiscRegClass:
-        panic("MiscRegs should not be read with getReg.");
-      default:
-        panic("Unrecognized register class type %d.", type);
-    }
-}
-
-void *
-ThreadContext::getWritableRegFlat(const RegId &reg)
-{
-    const RegIndex idx = reg.index();
-    const RegClassType type = reg.classValue();
-    switch (type) {
-      case VecRegClass:
-        return &getWritableVecRegFlat(idx);
-      case VecPredRegClass:
-        return &getWritableVecPredRegFlat(idx);
-      default:
-        panic("Unrecognized register class type %d.", type);
-    }
-}
-
-void
-ThreadContext::setRegFlat(const RegId &reg, const void *val)
-{
-    const RegIndex idx = reg.index();
-    const RegClassType type = reg.classValue();
-    switch (type) {
-      case IntRegClass:
-        setIntRegFlat(idx, *(RegVal *)val);
-        break;
-      case FloatRegClass:
-        setFloatRegFlat(idx, *(RegVal *)val);
-        break;
-      case VecRegClass:
-        setVecRegFlat(idx, *(TheISA::VecRegContainer *)val);
-        break;
-      case VecElemClass:
-        setVecElemFlat(idx, *(RegVal *)val);
-        break;
-      case VecPredRegClass:
-        setVecPredRegFlat(idx, *(TheISA::VecPredRegContainer *)val);
-        break;
-      case CCRegClass:
-        setCCRegFlat(idx, *(RegVal *)val);
-        break;
-      case MiscRegClass:
-        panic("MiscRegs should not be read with getReg.");
-      default:
-        panic("Unrecognized register class type %d.", type);
-    }
-}
-
-void
 serialize(const ThreadContext &tc, CheckpointOut &cp)
 {
     // Cast away the const so we can get the non-const ISA ptr, which we  
then
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 09cef3c..5e1c5ad 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -335,11 +335,11 @@
      */

     virtual RegVal getRegFlat(const RegId &reg) const;
-    virtual void getRegFlat(const RegId &reg, void *val) const;
-    virtual void *getWritableRegFlat(const RegId &reg);
+    virtual void getRegFlat(const RegId &reg, void *val) const = 0;
+    virtual void *getWritableRegFlat(const RegId &reg) = 0;

     virtual void setRegFlat(const RegId &reg, RegVal val);
-    virtual void setRegFlat(const RegId &reg, const void *val);
+    virtual void setRegFlat(const RegId &reg, const void *val) = 0;

     RegVal
     readIntRegFlat(RegIndex idx) const

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4135f0d8721f5f9d724be590767bed0023a9de20
Gerrit-Change-Number: 49698
Gerrit-PatchSet: 52
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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