Hello everyone, We (PLCT Labs) are adding support for the Vector extension to the gem5 RISC-V ISA. We are having some difficulty with memory access related instructions. Hope someone with experience on this can give some help.
In CPUs that use timing memory access, each Packet can only carry cache-line-sized data, and each instruction only calls the initiateAcc method once during the commit phase. So it doesn't seems possible to put memory data into one or more VecRegContainers or vice versa in one instruction. So turning a single memory access instruction into multiple micro-ops seems like a good option. The micro-ops needs to be split in the constructor of the macro-op, which will be called in the docode stage, and the parameter passed to the constructor are only the static instruction. However, in the Vector extension, the number of micro-ops that a memory access instruction needs to be split into is related to the VTYPE and VL registers. Depending on the values of VTYPE and VL, the same instruction may need to involve 1 to 8 VecRegContainers. We would like to know, in the current implementation of gem5, is there a way to read the value of the misc register during the decode phase? Yang Liu _______________________________________________ gem5-dev mailing list -- [email protected] To unsubscribe send an email to [email protected] %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
