Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/56593 )
Change subject: arch-arm: Reuse MCR15 trapping code in DC instructions
......................................................................
arch-arm: Reuse MCR15 trapping code in DC instructions
Change-Id: I08fec815400ad572da543660f0136e3d88d4dc65
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56593
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/arm/isa/insts/misc.isa
1 file changed, 21 insertions(+), 28 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa/insts/misc.isa
b/src/arch/arm/isa/insts/misc.isa
index c5ab3fa..72c8d68 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -967,7 +967,7 @@
exec_output += PredOpExecute.subst(mrc15Iop)
- mcr15code = '''
+ mcr15CheckCode = '''
int preFlatDest = snsBankedIndex(dest, xc->tcBase());
MiscRegIndex miscReg = (MiscRegIndex)
xc->tcBase()->flattenRegId(RegId(MiscRegClass,
@@ -989,6 +989,8 @@
if (fault != NoFault) {
return fault;
}
+ '''
+ mcr15code = mcr15CheckCode + '''
MiscNsBankedDest = Op1;
'''
mcr15Iop = ArmInstObjParams("mcr", "Mcr15", "MiscRegRegImmOp",
@@ -1110,29 +1112,6 @@
decoder_output += BasicConstructor.subst(clrexIop)
exec_output += PredOpExecute.subst(clrexIop)
- McrDcCheckCode = '''
- int preFlatDest = snsBankedIndex(dest, xc->tcBase());
- MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
- RegId(MiscRegClass, preFlatDest)).index();
-
- Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), imm);
-
- auto [can_write, undefined] = canWriteCoprocReg(miscReg, Scr, Cpsr,
- xc->tcBase());
-
- // if we're in non secure PL1 mode then we can trap regardless
- // of whether the register is accessible, in other modes we
- // trap if only if the register IS accessible.
- if (undefined || (!can_write && !(fault != NoFault
&& !inUserMode(Cpsr) &&
- !isSecure(xc->tcBase())))) {
- return std::make_shared<UndefinedInstruction>(machInst, false,
- mnemonic);
- }
- if (fault != NoFault) {
- return fault;
- }
- '''
-
McrDcimvacCode = '''
const Request::Flags memAccessFlags(Request::INVALIDATE |
Request::DST_POC);
@@ -1140,7 +1119,7 @@
'''
McrDcimvacIop = ArmInstObjParams("mcr", "McrDcimvac",
"MiscRegRegImmOp",
- {"memacc_code": McrDcCheckCode,
+ {"memacc_code": mcr15CheckCode,
"postacc_code": "",
"ea_code": McrDcimvacCode,
"predicate_test": predicateTest},
@@ -1158,7 +1137,7 @@
'''
McrDccmvacIop = ArmInstObjParams("mcr", "McrDccmvac",
"MiscRegRegImmOp",
- {"memacc_code": McrDcCheckCode,
+ {"memacc_code": mcr15CheckCode,
"postacc_code": "",
"ea_code": McrDccmvacCode,
"predicate_test": predicateTest},
@@ -1176,7 +1155,7 @@
'''
McrDccmvauIop = ArmInstObjParams("mcr", "McrDccmvau",
"MiscRegRegImmOp",
- {"memacc_code": McrDcCheckCode,
+ {"memacc_code": mcr15CheckCode,
"postacc_code": "",
"ea_code": McrDccmvauCode,
"predicate_test": predicateTest},
@@ -1195,7 +1174,7 @@
'''
McrDccimvacIop = ArmInstObjParams("mcr", "McrDccimvac",
"MiscRegRegImmOp",
- {"memacc_code": McrDcCheckCode,
+ {"memacc_code": mcr15CheckCode,
"postacc_code": "",
"ea_code": McrDccimvacCode,
"predicate_test": predicateTest},
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I08fec815400ad572da543660f0136e3d88d4dc65
Gerrit-Change-Number: 56593
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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