Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/56594 )
(
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: Implement DSB Shareable with a separate class
......................................................................
arch-arm: Implement DSB Shareable with a separate class
This is an initial step towards making DSB shareable issue a memory
operation (generating DVM messages)
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
Change-Id: Ia7225acc13008ba1ebdf0b091941f6b494e9d4d6
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56594
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/insts/misc64.isa
2 files changed, 44 insertions(+), 9 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa/formats/aarch64.isa
b/src/arch/arm/isa/formats/aarch64.isa
index 0c67645..3c30be6 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -1,4 +1,4 @@
-// Copyright (c) 2011-2020 ARM Limited
+// Copyright (c) 2011-2021 Arm Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -401,7 +401,16 @@
case 0x2:
return new Clrex64(machInst);
case 0x4:
- return new Dsb64(machInst);
+ switch (bits(crm, 3, 2)) {
+ case 0x1: // Non-Shareable
+ return new Dsb64Local(machInst);
+ case 0x0: // OuterShareable
+ case 0x2: // InnerShareable
+ case 0x3: // FullSystem
+ return new Dsb64Shareable(machInst);
+ default:
+ GEM5_UNREACHABLE;
+ }
case 0x5:
return new Dmb64(machInst);
case 0x6:
diff --git a/src/arch/arm/isa/insts/misc64.isa
b/src/arch/arm/isa/insts/misc64.isa
index d516c53..9151b88 100644
--- a/src/arch/arm/isa/insts/misc64.isa
+++ b/src/arch/arm/isa/insts/misc64.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2011-2013, 2016-2018, 2020 ARM Limited
+// Copyright (c) 2011-2013, 2016-2018, 2020-2021 Arm Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -172,12 +172,19 @@
decoder_output += BasicConstructor64.subst(isbIop)
exec_output += BasicExecute.subst(isbIop)
- dsbIop = ArmInstObjParams("dsb", "Dsb64", "ArmStaticInst", "",
- ['IsReadBarrier', 'IsWriteBarrier',
- 'IsSerializeAfter'])
- header_output += BasicDeclare.subst(dsbIop)
- decoder_output += BasicConstructor64.subst(dsbIop)
- exec_output += BasicExecute.subst(dsbIop)
+ dsbLocalIop =
ArmInstObjParams("dsb", "Dsb64Local", "ArmStaticInst", "",
+ ['IsReadBarrier', 'IsWriteBarrier',
+ 'IsSerializeAfter'])
+ header_output += BasicDeclare.subst(dsbLocalIop)
+ decoder_output += BasicConstructor64.subst(dsbLocalIop)
+ exec_output += BasicExecute.subst(dsbLocalIop)
+
+ dsbShareableIop =
ArmInstObjParams("dsb", "Dsb64Shareable", "ArmStaticInst", "",
+ ['IsReadBarrier', 'IsWriteBarrier',
+ 'IsSerializeAfter'])
+ header_output += BasicDeclare.subst(dsbShareableIop)
+ decoder_output += BasicConstructor64.subst(dsbShareableIop)
+ exec_output += BasicExecute.subst(dsbShareableIop)
dmbIop = ArmInstObjParams("dmb", "Dmb64", "ArmStaticInst", "",
['IsReadBarrier', 'IsWriteBarrier'])
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia7225acc13008ba1ebdf0b091941f6b494e9d4d6
Gerrit-Change-Number: 56594
Gerrit-PatchSet: 5
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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