Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/57291 )
Change subject: cpu: Handle external TLBI Sync requests in TimingCPU
......................................................................
cpu: Handle external TLBI Sync requests in TimingCPU
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
Change-Id: I4e92f7886a296f119720b8bcda6bea722df76153
---
M src/cpu/simple/timing.cc
1 file changed, 32 insertions(+), 3 deletions(-)
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 9e29cde..12ec3a5 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -1097,14 +1097,32 @@
}
// Making it uniform across all CPUs:
- // The CPUs need to be woken up only on an invalidation packet (when
using caches)
- // or on an incoming write packet (when not using caches)
- // It is not necessary to wake up the processor on all incoming packets
+ // The CPUs need to be woken up only on an invalidation packet
+ // (when using caches) or on an incoming write packet (when not
+ // using caches) It is not necessary to wake up the processor on
+ // all incoming packets
if (pkt->isInvalidate() || pkt->isWrite()) {
for (auto &t_info : cpu->threadInfo) {
t_info->thread->getIsaPtr()->handleLockedSnoop(pkt,
cacheBlockMask);
}
+ } else if (pkt->req && pkt->req->isTlbiExtSync()) {
+ // We received a TLBI_EXT_SYNC request.
+ // In a detailed sim we would wait for memory ops to complete,
+ // but in our simple case we just respond immediately
+ RequestPtr reply_req = std::make_shared<Request>(
+ 0, 8,
+ Request::TLBI_EXT_SYNC_COMP,
+ Request::funcRequestorId);
+
+ // Extra Data = the transaction ID of the Sync we're completing
+ reply_req->setExtraData(pkt->req->getExtraData());
+ PacketPtr reply_pkt = Packet::createRead(reply_req);
+
+ // TODO - reserve some credit for these responses?
+ if (!sendTimingReq(reply_pkt)) {
+ panic("Couldn't send TLBI_EXT_SYNC_COMP message");
+ }
}
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4e92f7886a296f119720b8bcda6bea722df76153
Gerrit-Change-Number: 57291
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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