Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/57296 )
Change subject: mem-ruby: Added upstream_nodes to AbstractController
......................................................................
mem-ruby: Added upstream_nodes to AbstractController
Added support for an upstream_nodes NetAddr list in AbstractController,
which will be used in future CHI work.
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
Change-Id: I30a6d621d7f201d89f0b13dab8ed4dd1f1f6caa3
---
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/ruby/slicc_interface/Controller.py
3 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc
b/src/mem/ruby/slicc_interface/AbstractController.cc
index 396b128..e11d780 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -108,7 +108,13 @@
}
downstreamDestinations.add(mid);
}
-
+ // Initialize the addr->upstream machine list.
+ // We do not need to map address -> upstream machine,
+ // so we don't examine the address ranges
+ upstreamDestinations.resize();
+ for (auto abs_cntrl : params().upstream_destinations) {
+ upstreamDestinations.add(abs_cntrl->getMachineID());
+ }
}
void
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh
b/src/mem/ruby/slicc_interface/AbstractController.hh
index 56c164f..9f4f75b 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -216,6 +216,8 @@
const NetDest& allDownstreamDest() const { return
downstreamDestinations; }
+ const NetDest& allUpstreamDest() const { return upstreamDestinations; }
+
protected:
//! Profiles original cache requests including PUTs
void profileRequest(const std::string &request);
@@ -375,6 +377,7 @@
AddrRangeMap<AddrMapEntry, 3> downstreamAddrMap;
NetDest downstreamDestinations;
+ NetDest upstreamDestinations;
public:
struct ControllerStats : public statistics::Group
diff --git a/src/mem/ruby/slicc_interface/Controller.py
b/src/mem/ruby/slicc_interface/Controller.py
index 15366de2..c73836d 100644
--- a/src/mem/ruby/slicc_interface/Controller.py
+++ b/src/mem/ruby/slicc_interface/Controller.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2017,2019,2020 ARM Limited
+# Copyright (c) 2017,2019-2021 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -75,5 +75,7 @@
# These can be used by a protocol to enable reuse of the same machine
# types to model different levels of the cache hierarchy
+ upstream_destinations = VectorParam.RubyController([],
+ "Possible destinations for requests sent towards the
CPU")
downstream_destinations = VectorParam.RubyController([],
"Possible destinations for requests sent towards
memory")
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I30a6d621d7f201d89f0b13dab8ed4dd1f1f6caa3
Gerrit-Change-Number: 57296
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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