Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/57299 )
Change subject: mem-ruby: CHI fix for WUs on local+upstream line
......................................................................
mem-ruby: CHI fix for WUs on local+upstream line
Fix for WriteUnique operations on cache lines that are both local and
upstream
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
Change-Id: I99def32948d3f0ced9cfc7f7712a0f4ae9aab0cd
---
M src/mem/ruby/protocol/chi/CHI-cache-actions.sm
M src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
2 files changed, 54 insertions(+), 1 deletion(-)
diff --git a/src/mem/ruby/protocol/chi/CHI-cache-actions.sm
b/src/mem/ruby/protocol/chi/CHI-cache-actions.sm
index 65182ae..d203db0 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache-actions.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache-actions.sm
@@ -280,6 +280,35 @@
}
}
+action(Initiate_Request_NoTagRead, desc="") {
+ State initial := getState(tbe, cache_entry, address);
+ bool was_retried := false;
+ peek(reqRdyPort, CHIRequestMsg) {
+ set_tbe(allocateRequestTBE(address, in_msg));
+ // only a msg that was already retried doesn't allow a retry
+ was_retried := in_msg.allowRetry == false;
+ }
+ DirEntry dir_entry := getDirEntry(address);
+ copyCacheAndDir(cache_entry, dir_entry, tbe, initial);
+
+ tbe.use_DMT := is_HN && enable_DMT;
+ tbe.use_DCT := enable_DCT;
+
+ bool alloc_entry := needCacheEntry(tbe.reqType,
+ cache_entry, dir_entry,
+ tbe.is_local_pf);
+ bool dealloc_entry := needDeallocCacheEntry(tbe.reqType);
+ assert((alloc_entry && dealloc_entry) == false);
+
+ // always drops any data when not caching it or when this transaction
+ // requires deallocation
+ tbe.dataToBeInvalid := dealloc_entry ||
+ (is_invalid(cache_entry) && (alloc_entry ==
false));
+ tbe.doCacheFill := alloc_entry || is_valid(cache_entry);
+
+ incomingTransactionStart(address, curTransitionEvent(), initial,
was_retried);
+}
+
action(Initiate_Request_Stale, desc="") {
State initial := getState(tbe, cache_entry, address);
bool was_retried := false;
diff --git a/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
b/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
index 101a34d..77b164a 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
@@ -347,7 +347,7 @@
// WriteUniquePtl
-transition({UD,UD_RU,UD_RSD,UD_RSC,UC,UC_RU,UC_RSC},
+transition({UD,UD_RSD,UD_RSC,UC,UC_RSC},
{WriteUnique, WriteUniquePtl_PoC, WriteUniqueFull_PoC,
WriteUniqueFull_PoC_Alloc},
BUSY_BLKD) {
Initiate_Request;
@@ -357,6 +357,16 @@
ProcessNextState;
}
+transition({UD_RU,UC_RU},
+ {WriteUnique, WriteUniquePtl_PoC, WriteUniqueFull_PoC,
WriteUniqueFull_PoC_Alloc},
+ BUSY_BLKD) {
+ Initiate_Request_NoTagRead;
+ Initiate_WriteUnique_LocalWrite;
+ Profile_Miss;
+ Pop_ReqRdyQueue;
+ ProcessNextState;
+}
+
transition({SD, SD_RSD, SD_RSC, SC, SC_RSC},
{WriteUniquePtl_PoC, WriteUniqueFull_PoC,
WriteUniqueFull_PoC_Alloc},
BUSY_BLKD) {
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I99def32948d3f0ced9cfc7f7712a0f4ae9aab0cd
Gerrit-Change-Number: 57299
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-CC: Tiago Muck <tiago.m...@arm.com>
Gerrit-MessageType: newchange
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