Rivos is working on adding RISC-V Vector support to Gem5. We've pushed the
initial set of changes to our public fork here:
https://github.com/rivosinc/gem5/commits/rivos/dev/joy/initial_RVV_support
We’d like to get feedback from the community and make the changes required
to get this merged into mainline Gem5.
Details:
The model builds with:
scons build/RISCV/gem5.opt
I made a few hacks to get things working. I’ve split these out as separate
commits (prefixed with HACK: ) detailed here:
commit d6d068c9fabf34e5327107513ec41dea3e5e9acc
Author: Jerin Joy <j...@rivosinc.com>
Date: Wed Mar 2 11:29:18 2022 -0800
HACK: rivos: to get the decoder to take vl and vtype
This adds the VTYPE and VL to the PCStateBase class. The decodeInst() now
gets passed the VL and VTYPE values. We need to know the contents of these
registers at decode time to determine how many source/destination registers
the instruction will operate on.
commit 13a2fdb11ba67ff8a880864e295b1440a9df7bac
Author: Jerin Joy <j...@rivosinc.com>
Date: Wed Mar 2 15:44:26 2022 -0800
HACK: rivos: Resize VecRegs to RiscvISA::NumVecRegs
VecRegs is a C++ Vector with 1 entry and needs to be resized to 32 entries.
commit 6fc2d233c0a2aaa93438b1386cc5ce177509b05d
Author: Jerin Joy <j...@rivosinc.com>
Date: Tue Mar 1 15:00:16 2022 -0800
wip - rivos: Adding RISCV_VLEN/ELEN as a SCons variable
We want to make the VLEN and ELEN configurable at build time. Ideally we’d
like to pick these up from build_opts/RISCV but I couldn’t get that to work
so this uses environment variables instead:
('RISCV_VLEN', "VLEN for RVV", environ.get('RISCV_VLEN', '1024')),
('RISCV_ELEN', "ELEN for RVV", environ.get('RISCV_ELEN', '128')),
env RISCV_VLEN=32768 RISCV_ELEN=1024 scons -j 10 build/RISCV/gem5.opt
I referenced the work of the PLCT lab from this thread to get started.
https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/aVxFnFW3WQw
Jerin
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