Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/57530 )
Change subject: dev-amdgpu: Always mark interrupts enabled
......................................................................
dev-amdgpu: Always mark interrupts enabled
The driver will check this bit is set after initializing IPs. Currently
the MMIO trace will cause this bit to be set at the correct time,
however this is not portable access different ROCm versions. Therefore
we modify the value to always set the bit indicating interrupts are
enabled.
Change-Id: Iae0baf1936720fbe9835ae4acadbf1b3bdc52896
---
M src/dev/amdgpu/amdgpu_device.cc
1 file changed, 29 insertions(+), 0 deletions(-)
diff --git a/src/dev/amdgpu/amdgpu_device.cc
b/src/dev/amdgpu/amdgpu_device.cc
index f559827..73ff971 100644
--- a/src/dev/amdgpu/amdgpu_device.cc
+++ b/src/dev/amdgpu/amdgpu_device.cc
@@ -214,6 +214,20 @@
mmioReader.readFromTrace(pkt, MMIO_BAR, offset);
switch (aperture) {
+ case NBIO_BASE:
+ switch (aperture_offset) {
+ // This is a PCIe status register. At some point during driver
init
+ // the driver checks that interrupts are enabled. This is only
+ // checked once, so if the MMIO trace does not exactly line up
with
+ // what the driver is doing in gem5, this may still have the
first
+ // bit zero causing driver to fail. Therefore, we always set this
+ // bit to one as there is no harm to do so.
+ case 0x3c: // mmPCIE_DATA2 << 2
+ uint32_t value = pkt->getLE<uint32_t>() | 0x1;
+ DPRINTF(AMDGPUDevice, "Marking interrupts enabled: %#lx\n",
value);
+ pkt->setLE<uint32_t>(value);
+ break;
+ } break;
case GRBM_BASE:
gpuvm.readMMIO(pkt, aperture_offset >> GRBM_OFFSET_SHIFT);
break;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iae0baf1936720fbe9835ae4acadbf1b3bdc52896
Gerrit-Change-Number: 57530
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-MessageType: newchange
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