蔡森至 has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/57850 )
Change subject: cpu-o3: Fix O3 lsq_unit index variables type
......................................................................
cpu-o3: Fix O3 lsq_unit index variables type
This patch fixes the problem about the type of index for O3 LSQueue
by replacing some variable's type "int" with "size_t" or "ssize_t".
This patch avoids O3 cpu model overflows 31-bite value leading to
unexpected error during huge program (e.g. spec2006) simulation.
Jira Issue:: https://gem5.atlassian.net/browse/GEM5-1203
Change-Id: I13884ec9872163f62ff8a3e1de9966832cd2d5dd
---
M src/cpu/o3/lsq_unit.cc
M src/cpu/o3/lsq_unit.hh
2 files changed, 35 insertions(+), 19 deletions(-)
diff --git a/src/cpu/o3/lsq_unit.cc b/src/cpu/o3/lsq_unit.cc
index 856cef3..649b6c0 100644
--- a/src/cpu/o3/lsq_unit.cc
+++ b/src/cpu/o3/lsq_unit.cc
@@ -190,7 +190,7 @@
}
}
-LSQUnit::LSQUnit(uint32_t lqEntries, uint32_t sqEntries)
+LSQUnit::LSQUnit(size_t lqEntries, size_t sqEntries)
: lsqID(-1), storeQueue(sqEntries), loadQueue(lqEntries),
storesToWB(0),
htmStarts(0), htmStops(0),
@@ -287,7 +287,7 @@
void
LSQUnit::drainSanityCheck() const
{
- for (int i = 0; i < loadQueue.capacity(); ++i)
+ for (size_t i = 0; i < loadQueue.capacity(); ++i)
assert(!loadQueue[i].valid());
assert(storesToWB == 0);
@@ -660,7 +660,7 @@
// Make sure that a store exists.
assert(storeQueue.size() != 0);
- int store_idx = store_inst->sqIdx;
+ ssize_t store_idx = store_inst->sqIdx;
DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n",
store_inst->pcState(), store_inst->seqNum);
@@ -969,7 +969,7 @@
if (scan_it->instruction()->isHtmStart() &&
!scan_it->instruction()->isSquashed()) {
in_flight_uid = scan_it->instruction()->getHtmTransactionUid();
- DPRINTF(HtmCpu, "loadQueue[%d]: found valid HtmStart
htmUid=%u\n",
+ DPRINTF(HtmCpu, "loadQueue[%ld]: found valid HtmStart
htmUid=%u\n",
scan_it._idx, in_flight_uid);
}
scan_it++;
@@ -1158,8 +1158,8 @@
iewStage->updateLSQNextCycle = true;
}
- DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
- "idx:%i\n",
+ DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%li, store head "
+ "idx:%li\n",
store_inst->seqNum, store_idx.idx() - 1, storeQueue.head() -
1);
#if TRACING_ON
@@ -1282,7 +1282,7 @@
}
Fault
-LSQUnit::read(LSQRequest *request, int load_idx)
+LSQUnit::read(LSQRequest *request, ssize_t load_idx)
{
LQEntry& load_entry = loadQueue[load_idx];
const DynInstPtr& load_inst = load_entry.instruction();
@@ -1318,8 +1318,8 @@
load_inst->seqNum, load_inst->pcState());
}
- DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "
- "storeHead: %i addr: %#x%s\n",
+ DPRINTF(LSQUnit, "Read called, load idx: %li, store idx: %li, "
+ "storeHead: %li addr: %#x%s\n",
load_idx - 1, load_inst->sqIt._idx, storeQueue.head() - 1,
request->mainReq()->getPaddr(), request->isSplit() ? " split" :
"");
@@ -1434,7 +1434,7 @@
store_it->data() + shift_amt,
request->mainReq()->getSize());
- DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
+ DPRINTF(LSQUnit, "Forwarding from store idx %li to load
to "
"addr %#x\n", store_it._idx,
request->mainReq()->getVaddr());
@@ -1567,11 +1567,11 @@
}
Fault
-LSQUnit::write(LSQRequest *request, uint8_t *data, int store_idx)
+LSQUnit::write(LSQRequest *request, uint8_t *data, ssize_t store_idx)
{
assert(storeQueue[store_idx].valid());
- DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x |
storeHead:%i "
+ DPRINTF(LSQUnit, "Doing write to store idx %li, addr %#x |
storeHead:%li "
"[sn:%llu]\n",
store_idx - 1, request->req()->getPaddr(), storeQueue.head() -
1,
storeQueue[store_idx].instruction()->seqNum);
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index e68cb53..d5a4796 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -101,7 +101,7 @@
/** The request. */
LSQRequest* _request = nullptr;
/** The size of the operation. */
- uint32_t _size = 0;
+ size_t _size = 0;
/** Valid entry. */
bool _valid = false;
@@ -141,8 +141,8 @@
/** Member accessors. */
/** @{ */
bool valid() const { return _valid; }
- uint32_t& size() { return _size; }
- const uint32_t& size() const { return _size; }
+ size_t& size() { return _size; }
+ const size_t& size() const { return _size; }
const DynInstPtr& instruction() const { return _inst; }
/** @} */
};
@@ -211,7 +211,7 @@
public:
/** Constructs an LSQ unit. init() must be called prior to use. */
- LSQUnit(uint32_t lqEntries, uint32_t sqEntries);
+ LSQUnit(size_t lqEntries, size_t sqEntries);
/** We cannot copy LSQUnit because it has stats for which copy
* contructor is deleted explicitly. However, STL vector requires
@@ -485,7 +485,7 @@
*/
InstSeqNum stallingStoreIsn;
/** The index of the above store. */
- int stallingLoadIdx;
+ size_t stallingLoadIdx;
/** The packet that needs to be retried. */
PacketPtr retryPkt;
@@ -539,10 +539,10 @@
public:
/** Executes the load at the given index. */
- Fault read(LSQRequest *request, int load_idx);
+ Fault read(LSQRequest *request, ssize_t load_idx);
/** Executes the store at the given index. */
- Fault write(LSQRequest *request, uint8_t *data, int store_idx);
+ Fault write(LSQRequest *request, uint8_t *data, ssize_t store_idx);
/** Returns the index of the head load instruction. */
int getLoadHead() { return loadQueue.head(); }
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I13884ec9872163f62ff8a3e1de9966832cd2d5dd
Gerrit-Change-Number: 57850
Gerrit-PatchSet: 1
Gerrit-Owner: 蔡森至 <a2215...@gmail.com>
Gerrit-MessageType: newchange
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