Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/58114 )
Change subject: arch-arm: Fix RW permission access for _EL12 registers
......................................................................
arch-arm: Fix RW permission access for _EL12 registers
_EL12 registers are supposed to be used in VHE only to access _EL1
registers. They are not accessible at EL1
Change-Id: I33c0a2b689e523d05712f0242da48e1b73580d6d
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58114
Reviewed-by: Andreas Sandberg <[email protected]>
Maintainer: Andreas Sandberg <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/arm/regs/misc.cc
1 file changed, 49 insertions(+), 16 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 9ceb67d..d1d8756 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2744,7 +2744,8 @@
| (LSMAOE ? 0 : 0x10000000))
.mapsTo(MISCREG_SCTLR_NS);
InitReg(MISCREG_SCTLR_EL12)
- .allPrivileges().exceptUserMode()
+ .monE2H()
+ .hypE2H()
.res0( 0x20440 | (EnDB ? 0 : 0x2000)
| (IESB ? 0 : 0x200000)
| (EnDA ? 0 : 0x8000000)
@@ -2761,7 +2762,8 @@
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_CPACR);
InitReg(MISCREG_CPACR_EL12)
- .allPrivileges().exceptUserMode()
+ .monE2H()
+ .hypE2H()
.mapsTo(MISCREG_CPACR_EL1);
InitReg(MISCREG_SCTLR_EL2)
.hyp().mon()
@@ -2815,19 +2817,22 @@
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_TTBR0_NS);
InitReg(MISCREG_TTBR0_EL12)
- .allPrivileges().exceptUserMode()
+ .monE2H()
+ .hypE2H()
.mapsTo(MISCREG_TTBR0_EL1);
InitReg(MISCREG_TTBR1_EL1)
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_TTBR1_NS);
InitReg(MISCREG_TTBR1_EL12)
- .allPrivileges().exceptUserMode()
+ .monE2H()
+ .hypE2H()
.mapsTo(MISCREG_TTBR1_EL1);
InitReg(MISCREG_TCR_EL1)
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_TTBCR_NS);
InitReg(MISCREG_TCR_EL12)
- .allPrivileges().exceptUserMode()
+ .monE2H()
+ .hypE2H()
.mapsTo(MISCREG_TTBCR_NS);
InitReg(MISCREG_TTBR0_EL2)
.hyp().mon()
@@ -2858,12 +2863,14 @@
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
InitReg(MISCREG_SPSR_EL12)
- .allPrivileges().exceptUserMode()
+ .monE2H()
+ .hypE2H()
.mapsTo(MISCREG_SPSR_SVC);
InitReg(MISCREG_ELR_EL1)
.allPrivileges().exceptUserMode();
InitReg(MISCREG_ELR_EL12)
- .allPrivileges().exceptUserMode()
+ .monE2H()
+ .hypE2H()
.mapsTo(MISCREG_ELR_EL1);
InitReg(MISCREG_SP_EL0)
.allPrivileges().exceptUserMode();
@@ -2914,18 +2921,21 @@
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_ADFSR_NS);
InitReg(MISCREG_AFSR0_EL12)
- .allPrivileges().exceptUserMode()
+ .monE2H()
+ .hypE2H()
.mapsTo(MISCREG_ADFSR_NS);
InitReg(MISCREG_AFSR1_EL1)
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_AIFSR_NS);
InitReg(MISCREG_AFSR1_EL12)
- .allPrivileges().exceptUserMode()
+ .monE2H()
+ .hypE2H()
.mapsTo(MISCREG_AIFSR_NS);
InitReg(MISCREG_ESR_EL1)
.allPrivileges().exceptUserMode();
InitReg(MISCREG_ESR_EL12)
- .allPrivileges().exceptUserMode()
+ .monE2H()
+ .hypE2H()
.mapsTo(MISCREG_ESR_EL1);
InitReg(MISCREG_IFSR32_EL2)
.hyp().mon()
@@ -2951,7 +2961,8 @@
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
InitReg(MISCREG_FAR_EL12)
- .allPrivileges().exceptUserMode()
+ .monE2H()
+ .hypE2H()
.mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
InitReg(MISCREG_FAR_EL2)
.hyp().mon()
@@ -3135,13 +3146,15 @@
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
InitReg(MISCREG_MAIR_EL12)
- .allPrivileges().exceptUserMode()
+ .monE2H()
+ .hypE2H()
.mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
InitReg(MISCREG_AMAIR_EL1)
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
InitReg(MISCREG_AMAIR_EL12)
- .allPrivileges().exceptUserMode()
+ .monE2H()
+ .hypE2H()
.mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
InitReg(MISCREG_MAIR_EL2)
.hyp().mon()
@@ -3161,7 +3174,8 @@
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_VBAR_NS);
InitReg(MISCREG_VBAR_EL12)
- .allPrivileges().exceptUserMode()
+ .monE2H()
+ .hypE2H()
.mapsTo(MISCREG_VBAR_NS);
InitReg(MISCREG_RVBAR_EL1)
.allPrivileges().exceptUserMode().writes(0);
@@ -3183,7 +3197,8 @@
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_CONTEXTIDR_NS);
InitReg(MISCREG_CONTEXTIDR_EL12)
- .allPrivileges().exceptUserMode()
+ .monE2H()
+ .hypE2H()
.mapsTo(MISCREG_CONTEXTIDR_NS);
InitReg(MISCREG_TPIDR_EL1)
.allPrivileges().exceptUserMode()
@@ -3899,7 +3914,8 @@
InitReg(MISCREG_ZCR_EL2)
.hyp().mon();
InitReg(MISCREG_ZCR_EL12)
- .allPrivileges().exceptUserMode()
+ .monE2H()
+ .hypE2H()
.mapsTo(MISCREG_ZCR_EL1);
InitReg(MISCREG_ZCR_EL1)
.allPrivileges().exceptUserMode();
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I33c0a2b689e523d05712f0242da48e1b73580d6d
Gerrit-Change-Number: 58114
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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