Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/55884 )
Change subject: arch-x86: Specialize LLDT for 64 bit and non-64 bit.
......................................................................
arch-x86: Specialize LLDT for 64 bit and non-64 bit.
In 64 bit mode the LLDT has a 128 bit descriptor which takes up two
slots. In any other mode, the descriptor is still 64 bits.
Change-Id: I88d3758a66dec3482153df5ec08565427d6c9269
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55884
Maintainer: Gabe Black <gabe.bl...@gmail.com>
Reviewed-by: Matt Sinclair <mattdsincl...@gmail.com>
Maintainer: Matt Sinclair <mattdsincl...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
M src/arch/x86/isa/insts/system/segmentation.py
2 files changed, 78 insertions(+), 24 deletions(-)
Approvals:
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index b82afb0..e993b18 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -48,7 +48,10 @@
0x00: decode MODRM_REG {
0x0: sldt_Mw_or_Rv();
0x1: str_Mw_or_Rv();
- 0x2: Inst::LLDT(Ew);
+ 0x2: decode MODE_SUBMODE {
+ 0x0: Inst::LLDT_64(Ew);
+ default: Inst::LLDT(Ew);
+ }
0x3: Inst::LTR(Ew);
0x4: verr_Mw_or_Rv();
0x5: verw_Mw_or_Rv();
diff --git a/src/arch/x86/isa/insts/system/segmentation.py
b/src/arch/x86/isa/insts/system/segmentation.py
index 814a32c..3915a73 100644
--- a/src/arch/x86/isa/insts/system/segmentation.py
+++ b/src/arch/x86/isa/insts/system/segmentation.py
@@ -211,6 +211,60 @@
st t1, tsg, [8, t4, t0], dataSize=8
};
+def macroop LLDT_64_R
+{
+ .serialize_after
+ chks reg, t0, InGDTCheck, flags=(EZF,)
+ br label("end"), flags=(CEZF,)
+ limm t4, 0, dataSize=8
+ srli t4, reg, 3, dataSize=2
+ ld t1, tsg, [8, t4, t0], dataSize=8
+ ld t2, tsg, [8, t4, t0], 8, dataSize=8
+ chks reg, t1, LDTCheck
+ wrdh t3, t1, t2
+ wrdl tsl, t1, reg
+ wrbase tsl, t3, dataSize=8
+end:
+ fault "NoFault"
+};
+
+def macroop LLDT_64_M
+{
+ .serialize_after
+ ld t5, seg, sib, disp, dataSize=2
+ chks t5, t0, InGDTCheck, flags=(EZF,)
+ br label("end"), flags=(CEZF,)
+ limm t4, 0, dataSize=8
+ srli t4, t5, 3, dataSize=2
+ ld t1, tsg, [8, t4, t0], dataSize=8
+ ld t2, tsg, [8, t4, t0], 8, dataSize=8
+ chks t5, t1, LDTCheck
+ wrdh t3, t1, t2
+ wrdl tsl, t1, t5
+ wrbase tsl, t3, dataSize=8
+end:
+ fault "NoFault"
+};
+
+def macroop LLDT_64_P
+{
+ .serialize_after
+ rdip t7
+ ld t5, seg, riprel, disp, dataSize=2
+ chks t5, t0, InGDTCheck, flags=(EZF,)
+ br label("end"), flags=(CEZF,)
+ limm t4, 0, dataSize=8
+ srli t4, t5, 3, dataSize=2
+ ld t1, tsg, [8, t4, t0], dataSize=8
+ ld t2, tsg, [8, t4, t0], 8, dataSize=8
+ chks t5, t1, LDTCheck
+ wrdh t3, t1, t2
+ wrdl tsl, t1, t5
+ wrbase tsl, t3, dataSize=8
+end:
+ fault "NoFault"
+};
+
def macroop LLDT_R
{
.serialize_after
@@ -218,12 +272,9 @@
br label("end"), flags=(CEZF,)
limm t4, 0, dataSize=8
srli t4, reg, 3, dataSize=2
- ldst t1, tsg, [8, t4, t0], dataSize=8
- ld t2, tsg, [8, t4, t0], 8, dataSize=8
+ ld t1, tsg, [8, t4, t0], dataSize=8
chks reg, t1, LDTCheck
- wrdh t3, t1, t2
wrdl tsl, t1, reg
- wrbase tsl, t3, dataSize=8
end:
fault "NoFault"
};
@@ -236,33 +287,16 @@
br label("end"), flags=(CEZF,)
limm t4, 0, dataSize=8
srli t4, t5, 3, dataSize=2
- ldst t1, tsg, [8, t4, t0], dataSize=8
- ld t2, tsg, [8, t4, t0], 8, dataSize=8
+ ld t1, tsg, [8, t4, t0], dataSize=8
chks t5, t1, LDTCheck
- wrdh t3, t1, t2
wrdl tsl, t1, t5
- wrbase tsl, t3, dataSize=8
end:
fault "NoFault"
};
def macroop LLDT_P
{
- .serialize_after
- rdip t7
- ld t5, seg, riprel, disp, dataSize=2
- chks t5, t0, InGDTCheck, flags=(EZF,)
- br label("end"), flags=(CEZF,)
- limm t4, 0, dataSize=8
- srli t4, t5, 3, dataSize=2
- ldst t1, tsg, [8, t4, t0], dataSize=8
- ld t2, tsg, [8, t4, t0], 8, dataSize=8
- chks t5, t1, LDTCheck
- wrdh t3, t1, t2
- wrdl tsl, t1, t5
- wrbase tsl, t3, dataSize=8
-end:
- fault "NoFault"
+ panic "LLDT in non-64 bit mode doesn't support RIP addressing."
};
def macroop SWAPGS
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I88d3758a66dec3482153df5ec08565427d6c9269
Gerrit-Change-Number: 55884
Gerrit-PatchSet: 13
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Bradford Beckmann <bradford.beckm...@gmail.com>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Matt Sinclair <mattdsincl...@gmail.com>
Gerrit-Reviewer: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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