Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/55886 )
Change subject: arch-x86: Specialize LTR for 64 bit mode.
......................................................................
arch-x86: Specialize LTR for 64 bit mode.
Like LDT descriptors, the TR descriptors are 128 bits in 64 bit mode,
and only 64 bits in other modes.
Change-Id: Iecfab8c5a90a8bfe0dff86880bc8f88c082ddc0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55886
Maintainer: Gabe Black <gabe.bl...@gmail.com>
Reviewed-by: Matt Sinclair <mattdsincl...@gmail.com>
Maintainer: Matt Sinclair <mattdsincl...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
M src/arch/x86/isa/insts/system/segmentation.py
2 files changed, 58 insertions(+), 4 deletions(-)
Approvals:
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index e993b18..c87b33e 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -52,7 +52,10 @@
0x0: Inst::LLDT_64(Ew);
default: Inst::LLDT(Ew);
}
- 0x3: Inst::LTR(Ew);
+ 0x3: decode MODE_SUBMODE {
+ 0x0: Inst::LTR_64(Ew);
+ default: Inst::LTR(Ew);
+ }
0x4: verr_Mw_or_Rv();
0x5: verw_Mw_or_Rv();
//0x6: jmpe_Ev(); // IA-64
diff --git a/src/arch/x86/isa/insts/system/segmentation.py
b/src/arch/x86/isa/insts/system/segmentation.py
index 3915a73..448f5c7 100644
--- a/src/arch/x86/isa/insts/system/segmentation.py
+++ b/src/arch/x86/isa/insts/system/segmentation.py
@@ -157,7 +157,7 @@
wrlimit idtr, t1
};
-def macroop LTR_R
+def macroop LTR_64_R
{
.serialize_after
chks reg, t0, TRCheck
@@ -174,7 +174,7 @@
st t1, tsg, [8, t4, t0], dataSize=8
};
-def macroop LTR_M
+def macroop LTR_64_M
{
.serialize_after
ld t5, seg, sib, disp, dataSize=2
@@ -192,7 +192,7 @@
st t1, tsg, [8, t4, t0], dataSize=8
};
-def macroop LTR_P
+def macroop LTR_64_P
{
.serialize_after
rdip t7
@@ -211,6 +211,40 @@
st t1, tsg, [8, t4, t0], dataSize=8
};
+def macroop LTR_R
+{
+ .serialize_after
+ chks reg, t0, TRCheck
+ limm t4, 0, dataSize=8
+ srli t4, reg, 3, dataSize=2
+ ldst t1, tsg, [8, t4, t0], dataSize=8
+ chks reg, t1, TSSCheck
+ wrdl tr, t1, reg
+ limm t5, (1 << 9)
+ or t1, t1, t5
+ st t1, tsg, [8, t4, t0], dataSize=8
+};
+
+def macroop LTR_M
+{
+ .serialize_after
+ ld t5, seg, sib, disp, dataSize=2
+ chks t5, t0, TRCheck
+ limm t4, 0, dataSize=8
+ srli t4, t5, 3, dataSize=2
+ ldst t1, tsg, [8, t4, t0], dataSize=8
+ chks t5, t1, TSSCheck
+ wrdl tr, t1, t5
+ limm t5, (1 << 9)
+ or t1, t1, t5
+ st t1, tsg, [8, t4, t0], dataSize=8
+};
+
+def macroop LTR_P
+{
+ panic "LTR in non-64 bit mode doesn't support RIP addressing."
+};
+
def macroop LLDT_64_R
{
.serialize_after
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iecfab8c5a90a8bfe0dff86880bc8f88c082ddc0e
Gerrit-Change-Number: 55886
Gerrit-PatchSet: 13
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Bradford Beckmann <bradford.beckm...@gmail.com>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Matt Sinclair <mattdsincl...@gmail.com>
Gerrit-Reviewer: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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