Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58511 )
Change subject: cpu, arch-arm: Rename initiateSpecialMemCmd to
initateMemMgmtCmd
......................................................................
cpu, arch-arm: Rename initiateSpecialMemCmd to initateMemMgmtCmd
This is aligning with the name of the generated memory requests
Change-Id: Ifdfa01477abf7ff597dce3b5cff78f9a27fdcbcc
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/insts/tme64ruby.cc
M src/arch/arm/isa/insts/data64.isa
M src/arch/arm/isa/insts/misc64.isa
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/o3/dyn_inst.cc
M src/cpu/o3/dyn_inst.hh
M src/cpu/simple/atomic.hh
M src/cpu/simple/base.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple/timing.cc
M src/cpu/simple/timing.hh
13 files changed, 35 insertions(+), 24 deletions(-)
diff --git a/src/arch/arm/insts/tme64ruby.cc
b/src/arch/arm/insts/tme64ruby.cc
index 3ddc735..b35433a 100644
--- a/src/arch/arm/insts/tme64ruby.cc
+++ b/src/arch/arm/insts/tme64ruby.cc
@@ -77,7 +77,7 @@
memAccessFlags = memAccessFlags | Request::NO_ACCESS;
}
- fault = xc->initiateSpecialMemCmd(memAccessFlags);
+ fault = xc->initiateMemMgmtCmd(memAccessFlags);
}
return fault;
@@ -175,7 +175,7 @@
Request::Flags memAccessFlags =
Request::STRICT_ORDER|Request::PHYSICAL|Request::HTM_CANCEL;
- fault = xc->initiateSpecialMemCmd(memAccessFlags);
+ fault = xc->initiateMemMgmtCmd(memAccessFlags);
return fault;
}
@@ -231,7 +231,7 @@
memAccessFlags = memAccessFlags | Request::NO_ACCESS;
}
- fault = xc->initiateSpecialMemCmd(memAccessFlags);
+ fault = xc->initiateMemMgmtCmd(memAccessFlags);
return fault;
}
diff --git a/src/arch/arm/isa/insts/data64.isa
b/src/arch/arm/isa/insts/data64.isa
index 5cf8b8a..922e923 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -383,7 +383,7 @@
Request::Flags memAccessFlags =
Request::STRICT_ORDER | Request::TLBI;
- fault = xc->initiateSpecialMemCmd(memAccessFlags);
+ fault = xc->initiateMemMgmtCmd(memAccessFlags);
PendingDvm = true;
}
diff --git a/src/arch/arm/isa/insts/misc64.isa
b/src/arch/arm/isa/insts/misc64.isa
index f98d894..abe30fc 100644
--- a/src/arch/arm/isa/insts/misc64.isa
+++ b/src/arch/arm/isa/insts/misc64.isa
@@ -188,7 +188,7 @@
memAccessFlags = memAccessFlags | Request::NO_ACCESS;
}
- fault = xc->initiateSpecialMemCmd(memAccessFlags);
+ fault = xc->initiateMemMgmtCmd(memAccessFlags);
PendingDvm = false;
}
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index cdb7f19..2ca32e6 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -242,7 +242,7 @@
};
Fault
- initiateSpecialMemCmd(Request::Flags flags) override
+ initiateMemMgmtCmd(Request::Flags flags) override
{
panic("not yet supported!");
return NoFault;
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index ece0c9c..5fb2cac 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -144,13 +144,13 @@
}
/**
- * Initiate a Special memory command with no valid address.
+ * Initiate a memory management command with no valid address.
* Currently, these instructions need to bypass squashing in the O3
model
* Examples include HTM commands and TLBI commands.
* e.g. tell Ruby we're starting/stopping a HTM transaction,
* or tell Ruby to issue a TLBI operation
*/
- virtual Fault initiateSpecialMemCmd(Request::Flags flags) = 0;
+ virtual Fault initiateMemMgmtCmd(Request::Flags flags) = 0;
/**
* For atomic-mode contexts, perform an atomic memory write operation.
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index c95550f..d9cf75f 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -116,9 +116,9 @@
}
Fault
- initiateSpecialMemCmd(Request::Flags flags) override
+ initiateMemMgmtCmd(Request::Flags flags) override
{
- panic("ExecContext::initiateSpecialMemCmd() not implemented "
+ panic("ExecContext::initiateMemMgmtCmd() not implemented "
" on MinorCPU\n");
return NoFault;
}
diff --git a/src/cpu/o3/dyn_inst.cc b/src/cpu/o3/dyn_inst.cc
index 8eb270a..0b9a900 100644
--- a/src/cpu/o3/dyn_inst.cc
+++ b/src/cpu/o3/dyn_inst.cc
@@ -410,7 +410,7 @@
}
Fault
-DynInst::initiateSpecialMemCmd(Request::Flags flags)
+DynInst::initiateMemMgmtCmd(Request::Flags flags)
{
const unsigned int size = 8;
return cpu->pushRequest(
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index d4ddb33..37f6c39 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -397,7 +397,7 @@
Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags,
const std::vector<bool> &byte_enable) override;
- Fault initiateSpecialMemCmd(Request::Flags flags) override;
+ Fault initiateMemMgmtCmd(Request::Flags flags) override;
Fault writeMem(uint8_t *data, unsigned size, Addr addr,
Request::Flags flags, uint64_t *res,
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index d7ab9c2..6fd790e 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -224,9 +224,9 @@
override;
Fault
- initiateSpecialMemCmd(Request::Flags flags) override
+ initiateMemMgmtCmd(Request::Flags flags) override
{
- panic("initiateSpecialMemCmd() is for timing accesses, and "
+ panic("initiateMemMgmtCmd() is for timing accesses, and "
"should never be called on AtomicSimpleCPU.\n");
}
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 4949ebc..4a56c74 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -191,14 +191,13 @@
void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
/**
- * Special memory commands such as hardware transactional memory
- * commands (HtmCmds) or TLBI commands, e.g. start a
- * transaction and commit a transaction, are memory operations but are
+ * Memory management commands such as hardware transactional memory
+ * commands or TLB invalidation commands are memory operations but are
* neither really (true) loads nor stores.
* For this reason the interface is extended,
- * and initiateSpecialMemCmd() is used to instigate the command.
+ * and initiateMemMgmtCmd() is used to instigate the command.
*/
- virtual Fault initiateSpecialMemCmd(Request::Flags flags) = 0;
+ virtual Fault initiateMemMgmtCmd(Request::Flags flags) = 0;
};
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 6f4e26b..443939c 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -446,9 +446,9 @@
}
Fault
- initiateSpecialMemCmd(Request::Flags flags) override
+ initiateMemMgmtCmd(Request::Flags flags) override
{
- return cpu->initiateSpecialMemCmd(flags);
+ return cpu->initiateMemMgmtCmd(flags);
}
/**
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 9e29cde..9ce7140 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -1216,7 +1216,7 @@
}
Fault
-TimingSimpleCPU::initiateSpecialMemCmd(Request::Flags flags)
+TimingSimpleCPU::initiateMemMgmtCmd(Request::Flags flags)
{
SimpleExecContext &t_info = *threadInfo[curThread];
SimpleThread* thread = t_info.thread;
@@ -1257,7 +1257,7 @@
DPRINTF(HtmCpu, "HTMcancel htmUid=%u\n",
t_info.getHtmTransactionUid());
else
- panic("initiateSpecialMemCmd: unknown HTM CMD");
+ panic("initiateMemMgmtCmd: unknown HTM CMD");
}
sendData(req, data, nullptr, true);
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 3dbdcad..ca6c0e2 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -325,7 +325,7 @@
void finishTranslation(WholeTranslationState *state);
/** hardware transactional memory & TLBI operations **/
- Fault initiateSpecialMemCmd(Request::Flags flags) override;
+ Fault initiateMemMgmtCmd(Request::Flags flags) override;
void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid,
HtmFailureFaultCause) override;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifdfa01477abf7ff597dce3b5cff78f9a27fdcbcc
Gerrit-Change-Number: 58511
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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