[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: Add CortexR52 artifact reset port

[Yu-hsin Wang (Gerrit) via gem5-dev]

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58813 )

Change subject: fastmodel: Add CortexR52 artifact reset port
......................................................................

fastmodel: Add CortexR52 artifact reset port

The artifact reset is an aggregated logic to reset the whole model. The
port helps us to simulate the reboot process.

Change-Id: I15101bfe11dee40b63cc29c2befb610beb3d32aa
---
M src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
4 files changed, 35 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py  
b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
index 615935e..151ed11 100644
--- a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
+++ b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
@@ -30,6 +30,7 @@
 from m5.objects.ArmInterrupts import ArmInterrupts
 from m5.objects.ArmISA import ArmISA
 from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
+from m5.objects.FastModelResetPort import FastModelResetResponsePort
 from m5.objects.IntPin import IntSinkPin, VectorIntSinkPin
 from m5.objects.Iris import IrisBaseCPU
 from m5.objects.SystemC import SystemC_ScModule
@@ -116,6 +117,8 @@
     top_reset = IntSinkPin('This signal resets timer and interrupt  
controller.')
     dbg_reset = IntSinkPin('Initialize the shared debug APB, Cross  
Trigger ' \
             'Interface (CTI), and Cross Trigger Matrix (CTM) logic.')
+    artifact_reset = FastModelResetResponsePort(
+        'An artifact reset port to reset the whole cluster.')

     CLUSTER_ID = Param.UInt16(0, "CLUSTER_ID[15:8] equivalent to " \
             "CFGMPIDRAFF2, CLUSTER_ID[7:0] equivalent to CFGMPIDRAFF1")
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc  
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
index 2b92b2a..d4d7c87 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
@@ -159,7 +159,7 @@
     if (if_name == "spi") {
         return evs->gem5_getPort(if_name, idx);
     } else if (if_name == "ext_slave" || if_name == "top_reset" ||
-               if_name == "dbg_reset") {
+               if_name == "dbg_reset" || if_name == "artifact_reset") {
         assert(idx == InvalidPortID);
         return evs->gem5_getPort(if_name, idx);
     } else {
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc  
b/src/arch/arm/fastmodel/CortexR52/evs.cc
index f9f1583..3dfc0af 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -99,6 +99,7 @@
     ext_slave(Base::ext_slave, p.name + ".ext_slave", -1),
     top_reset(p.name + ".top_reset", 0),
     dbg_reset(p.name + ".dbg_reset", 0),
+    artifact_reset(p.name + ".artifact_reset", -1, this),
     params(p)
 {
     for (int i = 0; i < CoreCount; i++)
@@ -148,6 +149,8 @@
         return this->top_reset;
     } else if (if_name == "dbg_reset") {
         return this->dbg_reset;
+    } else if (if_name == "artifact_reset") {
+        return this->artifact_reset;
     } else if (if_name == "spi") {
         return *this->spis.at(idx);
     } else if (if_name.substr(0, 3) == "ppi") {
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh  
b/src/arch/arm/fastmodel/CortexR52/evs.hh
index eee44c7..50c0d18 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -31,6 +31,7 @@
 #include <memory>

 #include "arch/arm/fastmodel/amba_ports.hh"
+#include "arch/arm/fastmodel/common/reset_port.hh"
 #include "arch/arm/fastmodel/common/signal_receiver.hh"
 #include "arch/arm/fastmodel/common/signal_sender.hh"
 #include "arch/arm/fastmodel/iris/cpu.hh"
@@ -125,6 +126,8 @@

     SignalSender dbg_reset;

+    ResetResponsePort<ScxEvsCortexR52> artifact_reset;
+
     CortexR52Cluster *gem5CpuCluster;

     const Params &params;
@@ -145,6 +148,19 @@
         this->signalInterrupt->spi(num, false);
     }

+    void
+    requestReset()
+    {
+        // Reset all cores.
+        for (auto &core_pin : corePins) {
+            core_pin->poweron_reset.signal_out.set_state(0, true);
+        }
+        // Reset L2 system.
+        this->top_reset.signal_out.set_state(0, true);
+        // Reset debug APB.
+        this->dbg_reset.signal_out.set_state(0, true);
+    }
+
     Port &gem5_getPort(const std::string &if_name, int idx) override;

     void

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I15101bfe11dee40b63cc29c2befb610beb3d32aa
Gerrit-Change-Number: 58813
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang <yuhsi...@google.com>
Gerrit-MessageType: newchange
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