Sascha Bischoff has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/64332?usp=email )
Change subject: cpu-o3: Remove obsolete getRegIds and getTrueId
......................................................................
cpu-o3: Remove obsolete getRegIds and getTrueId
These have been obsolete since
https://gem5-review.googlesource.com/c/public/gem5/+/49147, hence
removing.
Change-Id: I06f6c3058f652907d996b9e6267888e2d991622a
---
M src/cpu/o3/regfile.cc
M src/cpu/o3/regfile.hh
2 files changed, 13 insertions(+), 56 deletions(-)
diff --git a/src/cpu/o3/regfile.cc b/src/cpu/o3/regfile.cc
index fecb891..dcb8f70 100644
--- a/src/cpu/o3/regfile.cc
+++ b/src/cpu/o3/regfile.cc
@@ -175,47 +175,5 @@
freeList->addRegs(ccRegIds.begin(), ccRegIds.end());
}
-PhysRegFile::IdRange
-PhysRegFile::getRegIds(RegClassType cls)
-{
- switch (cls)
- {
- case IntRegClass:
- return std::make_pair(intRegIds.begin(), intRegIds.end());
- case FloatRegClass:
- return std::make_pair(floatRegIds.begin(), floatRegIds.end());
- case VecRegClass:
- return std::make_pair(vecRegIds.begin(), vecRegIds.end());
- case VecElemClass:
- return std::make_pair(vecElemIds.begin(), vecElemIds.end());
- case VecPredRegClass:
- return std::make_pair(vecPredRegIds.begin(), vecPredRegIds.end());
- case CCRegClass:
- return std::make_pair(ccRegIds.begin(), ccRegIds.end());
- case MiscRegClass:
- return std::make_pair(miscRegIds.begin(), miscRegIds.end());
- case InvalidRegClass:
- panic("Tried to get register IDs for the invalid class.");
- }
- /* There is no way to make an empty iterator */
- return std::make_pair(PhysIds::iterator(),
- PhysIds::iterator());
-}
-
-PhysRegIdPtr
-PhysRegFile::getTrueId(PhysRegIdPtr reg)
-{
- switch (reg->classValue()) {
- case VecRegClass:
- return &vecRegIds[reg->index()];
- case VecElemClass:
- return &vecElemIds[reg->index()];
- default:
- panic_if(!reg->is(VecElemClass),
- "Trying to get the register of a %s register",
reg->className());
- }
- return nullptr;
-}
-
} // namespace o3
} // namespace gem5
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 3ddf1a2..0130c55 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -309,20 +309,6 @@
panic("Unrecognized register class type %d.", type);
}
}
-
- /**
- * Get the PhysRegIds of the elems of all vector registers.
- * Auxiliary function to transition from Full vector mode to Elem mode
- * and to initialise the rename map.
- */
- IdRange getRegIds(RegClassType cls);
-
- /**
- * Get the true physical register id.
- * As many parts work with PhysRegIdPtr, we need to be able to produce
- * the pointer out of just class and register idx.
- */
- PhysRegIdPtr getTrueId(PhysRegIdPtr reg);
};
} // namespace o3
--
To view, visit
https://gem5-review.googlesource.com/c/public/gem5/+/64332?usp=email
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I06f6c3058f652907d996b9e6267888e2d991622a
Gerrit-Change-Number: 64332
Gerrit-PatchSet: 1
Gerrit-Owner: Sascha Bischoff <sascha.bisch...@arm.com>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
