Yu-hsin Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/64651?usp=email )
Change subject: fastmodel: improve debug message for resource not found
......................................................................
fastmodel: improve debug message for resource not found
The conversion logic between gem5 register id and iris resouce id is
duplicated in read and write function. Some of them also doens't handle
the invalid id correctly. This change wrapped the logic, fixed them, and
improved the debug message by printing the register names.
Change-Id: I093d05f5f06d804d5f01988c2a7ffa60244c5516
---
M src/arch/arm/fastmodel/iris/thread_context.cc
M src/arch/arm/fastmodel/iris/thread_context.hh
2 files changed, 117 insertions(+), 34 deletions(-)
diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc
b/src/arch/arm/fastmodel/iris/thread_context.cc
index d1aa041..27d4099 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -41,6 +41,7 @@
#include <cstdint>
#include <cstring>
+#include <sstream>
#include <utility>
#include <vector>
@@ -604,11 +605,25 @@
call().resource_write(_instId, result, pcRscId, pc);
}
+iris::ResourceId
+ThreadContext::getMiscRegRscId(RegIndex misc_reg) const
+{
+ iris::ResourceId rsc_id =
+ (misc_reg >= miscRegIds.size()) ? iris::IRIS_UINT64_MAX :
+ miscRegIds.at(misc_reg);
+ if (rsc_id == iris::IRIS_UINT64_MAX) {
+ std::stringstream ss;
+ ss << ArmISA::miscRegClass[misc_reg];
+ panic("Misc reg %s is not supported by fast model.",
ss.str().c_str());
+ }
+ return rsc_id;
+}
+
RegVal
ThreadContext::readMiscRegNoEffect(RegIndex misc_reg) const
{
iris::ResourceReadResult result;
- call().resource_read(_instId, result, miscRegIds.at(misc_reg));
+ call().resource_read(_instId, result, getMiscRegRscId(misc_reg));
return result.data.at(0);
}
@@ -616,7 +631,7 @@
ThreadContext::setMiscRegNoEffect(RegIndex misc_reg, const RegVal val)
{
iris::ResourceWriteResult result;
- call().resource_write(_instId, result, miscRegIds.at(misc_reg), val);
+ call().resource_write(_instId, result, getMiscRegRscId(misc_reg), val);
}
RegVal
@@ -766,29 +781,44 @@
}
}
+iris::ResourceId
+ThreadContext::getIntRegRscId(RegIndex int_reg) const
+{
+ ArmISA::CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
+ auto ®Ids = cpsr.width ? intReg32Ids : intReg64Ids;
+ iris::ResourceId rsc_id =
+ (int_reg >= regIds.size()) ? iris::IRIS_UINT64_MAX :
+ regIds.at(int_reg);
+ if (rsc_id == iris::IRIS_UINT64_MAX) {
+ std::stringstream ss;
+ ss << ArmISA::intRegClass[int_reg];
+ panic("Int reg %s is not supported by fast model.",
ss.str().c_str());
+ }
+ return rsc_id;
+}
+
RegVal
ThreadContext::readIntReg(RegIndex reg_idx) const
{
- ArmISA::CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
-
iris::ResourceReadResult result;
- if (cpsr.width)
- call().resource_read(_instId, result, intReg32Ids.at(reg_idx));
- else
- call().resource_read(_instId, result, intReg64Ids.at(reg_idx));
+ call().resource_read(_instId, result, getIntRegRscId(reg_idx));
return result.data.at(0);
}
void
ThreadContext::setIntReg(RegIndex reg_idx, RegVal val)
{
- ArmISA::CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
-
iris::ResourceWriteResult result;
- if (cpsr.width)
- call().resource_write(_instId, result, intReg32Ids.at(reg_idx),
val);
- else
- call().resource_write(_instId, result, intReg64Ids.at(reg_idx),
val);
+ call().resource_write(_instId, result, getIntRegRscId(reg_idx), val);
+}
+
+iris::ResourceId
+ThreadContext::getIntRegFlatRscId(RegIndex int_reg) const
+{
+ iris::ResourceId rsc_id =
+ (int_reg >= flattenedIntIds.size()) ? iris::IRIS_UINT64_MAX :
+ flattenedIntIds.at(int_reg);
+ return rsc_id;
}
/*
@@ -798,45 +828,67 @@
RegVal
ThreadContext::readIntRegFlat(RegIndex idx) const
{
- if (idx >= flattenedIntIds.size())
- return 0;
- iris::ResourceId res_id = flattenedIntIds.at(idx);
- if (res_id == iris::IRIS_UINT64_MAX)
+ auto rsc_id = getIntRegFlatRscId(idx);
+ if (rsc_id == iris::IRIS_UINT64_MAX)
return 0;
iris::ResourceReadResult result;
- call().resource_read(_instId, result, res_id);
+ call().resource_read(_instId, result, rsc_id);
return result.data.at(0);
}
void
ThreadContext::setIntRegFlat(RegIndex idx, uint64_t val)
{
- iris::ResourceId res_id =
- (idx >= flattenedIntIds.size()) ? iris::IRIS_UINT64_MAX :
- flattenedIntIds.at(idx);
- panic_if(res_id == iris::IRIS_UINT64_MAX,
- "Int reg %d is not supported by fast model.", idx);
+ auto rsc_id = getIntRegFlatRscId(idx);
+ if (rsc_id == iris::IRIS_UINT64_MAX) {
+ std::stringstream ss;
+ ss << ArmISA::intRegClass[idx];
+ panic("Int reg %s is not supported by fast model.",
ss.str().c_str());
+ }
iris::ResourceWriteResult result;
- call().resource_write(_instId, result, flattenedIntIds.at(idx), val);
+ call().resource_write(_instId, result, rsc_id, val);
+}
+
+iris::ResourceId
+ThreadContext::getCCRegFlatRscId(RegIndex cc_reg) const
+{
+ iris::ResourceId rsc_id =
+ (cc_reg >= ccRegIds.size()) ? iris::IRIS_UINT64_MAX :
+ ccRegIds.at(cc_reg);
+ return rsc_id;
}
RegVal
ThreadContext::readCCRegFlat(RegIndex idx) const
{
- if (idx >= ccRegIds.size())
+ auto rsc_id = getCCRegFlatRscId(idx);
+ if (rsc_id == iris::IRIS_UINT64_MAX)
return 0;
iris::ResourceReadResult result;
- call().resource_read(_instId, result, ccRegIds.at(idx));
+ call().resource_read(_instId, result, rsc_id);
return result.data.at(0);
}
void
ThreadContext::setCCRegFlat(RegIndex idx, RegVal val)
{
- panic_if(idx >= ccRegIds.size(),
- "CC reg %d is not supported by fast model.", idx);
+ auto rsc_id = getCCRegFlatRscId(idx);
+ if (rsc_id == iris::IRIS_UINT64_MAX) {
+ std::stringstream ss;
+ ss << ArmISA::ccRegClass[idx];
+ panic("CC reg %s is not supported by fast model.",
ss.str().c_str());
+ }
iris::ResourceWriteResult result;
- call().resource_write(_instId, result, ccRegIds.at(idx), val);
+ call().resource_write(_instId, result, rsc_id, val);
+}
+
+iris::ResourceId
+ThreadContext::getVecRegRscId(RegIndex vec_reg) const
+{
+ iris::ResourceId rsc_id =
+ (vec_reg >= vecRegIds.size()) ? iris::IRIS_UINT64_MAX :
+ vecRegIds.at(vec_reg);
+ return rsc_id;
}
const ArmISA::VecRegContainer &
@@ -849,11 +901,12 @@
// Ignore accesses to registers which aren't architected. gem5 defines
a
// few extra registers which it uses internally in the implementation
of
// some instructions.
- if (idx >= vecRegIds.size())
+ auto rsc_id = getVecRegRscId(reg_id);
+ if (rsc_id == iris::IRIS_UINT64_MAX)
return reg;
iris::ResourceReadResult result;
- call().resource_read(_instId, result, vecRegIds.at(idx));
+ call().resource_read(_instId, result, rsc_id);
size_t data_size = result.data.size() * (sizeof(*result.data.data()));
size_t size = std::min(data_size, reg.size());
memcpy(reg.as<uint8_t>(), (void *)result.data.data(), size);
@@ -867,6 +920,15 @@
return readVecReg(ArmISA::vecRegClass[idx]);
}
+iris::ResourceId
+ThreadContext::getVecPredRegRscId(RegIndex vec_reg) const
+{
+ iris::ResourceId rsc_id =
+ (vec_reg >= vecPredRegIds.size()) ? iris::IRIS_UINT64_MAX :
+ vecPredRegIds.at(vec_reg);
+ return rsc_id;
+}
+
const ArmISA::VecPredRegContainer &
ThreadContext::readVecPredReg(const RegId ®_id) const
{
@@ -875,11 +937,12 @@
ArmISA::VecPredRegContainer ® = vecPredRegs.at(idx);
reg.reset();
- if (idx >= vecPredRegIds.size())
+ auto rsc_id = getVecPredRegRscId(reg_id);
+ if (rsc_id == iris::IRIS_UINT64_MAX)
return reg;
iris::ResourceReadResult result;
- call().resource_read(_instId, result, vecPredRegIds.at(idx));
+ call().resource_read(_instId, result, rsc_id);
size_t offset = 0;
size_t num_bits = reg.NUM_BITS;
diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh
b/src/arch/arm/fastmodel/iris/thread_context.hh
index d289ed2..05209e6 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -286,8 +286,10 @@
void setReg(const RegId ®, RegVal val) override;
void setReg(const RegId ®, const void *val) override;
+ iris::ResourceId getIntRegRscId(RegIndex int_reg) const;
virtual RegVal readIntReg(RegIndex reg_idx) const;
+ iris::ResourceId getVecRegRscId(RegIndex vec_reg) const;
virtual const ArmISA::VecRegContainer &readVecReg(const RegId ®)
const;
virtual ArmISA::VecRegContainer &
getWritableVecReg(const RegId ®)
@@ -301,6 +303,7 @@
panic("%s not implemented.", __FUNCTION__);
}
+ iris::ResourceId getVecPredRegRscId(RegIndex vec_reg) const;
virtual const ArmISA::VecPredRegContainer &
readVecPredReg(const RegId ®) const;
virtual ArmISA::VecPredRegContainer &
@@ -347,6 +350,7 @@
const PCStateBase &pcState() const override;
void pcState(const PCStateBase &val) override;
+ iris::ResourceId getMiscRegRscId(RegIndex misc_reg) const;
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override;
RegVal
readMiscReg(RegIndex misc_reg) override
@@ -387,6 +391,7 @@
* serialization code to access all registers.
*/
+ iris::ResourceId getIntRegFlatRscId(RegIndex int_reg) const;
virtual RegVal readIntRegFlat(RegIndex idx) const;
virtual void setIntRegFlat(RegIndex idx, uint64_t val);
@@ -426,6 +431,7 @@
panic("%s not implemented.", __FUNCTION__);
}
+ iris::ResourceId getCCRegFlatRscId(RegIndex cc_reg) const;
virtual RegVal readCCRegFlat(RegIndex idx) const;
virtual void setCCRegFlat(RegIndex idx, RegVal val);
/** @} */
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I093d05f5f06d804d5f01988c2a7ffa60244c5516
Gerrit-Change-Number: 64651
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang <yuhsi...@google.com>
Gerrit-MessageType: newchange
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