Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/65091?usp=email )
Change subject: dev-amdgpu: Fix GART PTE size
......................................................................
dev-amdgpu: Fix GART PTE size
The GART table is a legacy 1-level page table primarily used for
supervisor mode accesses to GPUs. The PTE size is 64-bits, not 32-bit.
This causes memory sizes >3GB (in X86) to fail loading amdgpu driver.
This changeset fixes the issue by setting the GART mappings to the
correct data type.
Change-Id: Ibfba2443675fe28316d26afa5f1a14885fdce40c
---
M src/dev/amdgpu/amdgpu_device.cc
M src/dev/amdgpu/amdgpu_vm.hh
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/src/dev/amdgpu/amdgpu_device.cc
b/src/dev/amdgpu/amdgpu_device.cc
index 227e69e..2b58b20 100644
--- a/src/dev/amdgpu/amdgpu_device.cc
+++ b/src/dev/amdgpu/amdgpu_device.cc
@@ -270,7 +270,7 @@
// Record the value
if (aperture == gpuvm.gartBase()) {
- gpuvm.gartTable[aperture_offset] = pkt->getLE<uint32_t>();
+ gpuvm.gartTable[aperture_offset] =
pkt->getUintX(ByteOrder::little);
DPRINTF(AMDGPUDevice, "GART translation %p -> %p\n",
aperture_offset,
gpuvm.gartTable[aperture_offset]);
}
diff --git a/src/dev/amdgpu/amdgpu_vm.hh b/src/dev/amdgpu/amdgpu_vm.hh
index 8df169b..212a688 100644
--- a/src/dev/amdgpu/amdgpu_vm.hh
+++ b/src/dev/amdgpu/amdgpu_vm.hh
@@ -165,7 +165,7 @@
* Copy of GART table. Typically resides in device memory, however we
use
* a copy in gem5 to simplify the interface.
*/
- std::unordered_map<uint64_t, uint32_t> gartTable;
+ std::unordered_map<uint64_t, uint64_t> gartTable;
void readMMIO(PacketPtr pkt, Addr offset);
void writeMMIO(PacketPtr pkt, Addr offset);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibfba2443675fe28316d26afa5f1a14885fdce40c
Gerrit-Change-Number: 65091
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-MessageType: newchange
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