Roger Chang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/65532?usp=email )
Change subject: Add rv32 Syscall ABI
......................................................................
Add rv32 Syscall ABI
1. Change default value of arch to Unknown
2. Add RegABI32, SyscallABI32
3. Implement function arguments and results assignment with registers
4. Add write to ThreadPointerReg in archClone
Change-Id: Ie327b517f41b5d633d2741b6abb5be955281c838
---
M src/arch/riscv/linux/linux.hh
M src/arch/riscv/linux/se_workload.cc
M src/arch/riscv/linux/se_workload.hh
M src/arch/riscv/reg_abi.cc
M src/arch/riscv/reg_abi.hh
M src/arch/riscv/se_workload.hh
6 files changed, 67 insertions(+), 7 deletions(-)
diff --git a/src/arch/riscv/linux/linux.hh b/src/arch/riscv/linux/linux.hh
index b072183..fc651cb 100644
--- a/src/arch/riscv/linux/linux.hh
+++ b/src/arch/riscv/linux/linux.hh
@@ -371,6 +371,8 @@
uint64_t stack, uint64_t tls)
{
ctc->getIsaPtr()->copyRegsFrom(ptc);
+ if (flags & TGT_CLONE_SETTLS)
+ ctc->setReg(RiscvISA::ThreadPointerReg, sext<32>(tls));
if (stack)
ctc->setReg(RiscvISA::StackPointerReg, stack);
}
diff --git a/src/arch/riscv/linux/se_workload.cc
b/src/arch/riscv/linux/se_workload.cc
index dac2807..952fe71 100644
--- a/src/arch/riscv/linux/se_workload.cc
+++ b/src/arch/riscv/linux/se_workload.cc
@@ -123,7 +123,7 @@
return 0;
}
-SyscallDescTable<SEWorkload::SyscallABI> EmuLinux::syscallDescs64 = {
+SyscallDescTable<SEWorkload::SyscallABI64> EmuLinux::syscallDescs64 = {
{ 0, "io_setup" },
{ 1, "io_destroy" },
{ 2, "io_submit" },
@@ -462,7 +462,7 @@
{ 2011, "getmainvars" }
};
-SyscallDescTable<SEWorkload::SyscallABI> EmuLinux::syscallDescs32 = {
+SyscallDescTable<SEWorkload::SyscallABI32> EmuLinux::syscallDescs32 = {
{ 0, "io_setup" },
{ 1, "io_destroy" },
{ 2, "io_submit" },
diff --git a/src/arch/riscv/linux/se_workload.hh
b/src/arch/riscv/linux/se_workload.hh
index 41a3d41..4ec818b 100644
--- a/src/arch/riscv/linux/se_workload.hh
+++ b/src/arch/riscv/linux/se_workload.hh
@@ -47,10 +47,10 @@
protected:
/// 64 bit syscall descriptors, indexed by call number.
- static SyscallDescTable<SEWorkload::SyscallABI> syscallDescs64;
+ static SyscallDescTable<SEWorkload::SyscallABI64> syscallDescs64;
/// 32 bit syscall descriptors, indexed by call number.
- static SyscallDescTable<SEWorkload::SyscallABI> syscallDescs32;
+ static SyscallDescTable<SEWorkload::SyscallABI32> syscallDescs32;
public:
using Params = RiscvEmuLinuxParams;
diff --git a/src/arch/riscv/reg_abi.cc b/src/arch/riscv/reg_abi.cc
index b9827f7..3d48056 100644
--- a/src/arch/riscv/reg_abi.cc
+++ b/src/arch/riscv/reg_abi.cc
@@ -39,5 +39,11 @@
int_reg::A4, int_reg::A5, int_reg::A6
};
+const std::vector<RegId> RegABI32::ArgumentRegs = {
+ int_reg::A0, int_reg::A1, int_reg::A2, int_reg::A3,
+ int_reg::A4, int_reg::A5, int_reg::A6
+};
+
+
} // namespace RiscvISA
} // namespace gem5
diff --git a/src/arch/riscv/reg_abi.hh b/src/arch/riscv/reg_abi.hh
index 3419c31..ee94698 100644
--- a/src/arch/riscv/reg_abi.hh
+++ b/src/arch/riscv/reg_abi.hh
@@ -44,6 +44,11 @@
static const std::vector<RegId> ArgumentRegs;
};
+struct RegABI32 : public GenericSyscallABI32
+{
+ static const std::vector<RegId> ArgumentRegs;
+};
+
} // namespace RiscvISA
} // namespace gem5
diff --git a/src/arch/riscv/se_workload.hh b/src/arch/riscv/se_workload.hh
index 6f7c2ed..a8a0248 100644
--- a/src/arch/riscv/se_workload.hh
+++ b/src/arch/riscv/se_workload.hh
@@ -58,10 +58,11 @@
params().remote_gdb_port, system);
}
- loader::Arch getArch() const override { return loader::Riscv64; }
+ loader::Arch getArch() const override { return loader::UnknownArch; }
//FIXME RISCV needs to handle 64 bit arguments in its 32 bit ISA.
- using SyscallABI = RegABI64;
+ using SyscallABI64 = RegABI64;
+ using SyscallABI32 = RegABI32;
};
} // namespace RiscvISA
@@ -70,8 +71,40 @@
namespace guest_abi
{
+template <typename ABI, typename Arg>
+struct Argument<ABI, Arg,
+ typename std::enable_if_t<
+ std::is_base_of_v<RiscvISA::RegABI32, ABI> &&
+ std::is_integral_v<Arg> &&
+ ABI::template IsWideV<Arg>>>
+{
+ static Arg
+ get(ThreadContext *tc, typename ABI::State &state)
+ {
+ panic_if(state >= ABI::ArgumentRegs.size(),
+ "Ran out of syscall argument registers.");
+ return bits(tc->getReg(ABI::ArgumentRegs[state++]), 31, 0);
+ }
+};
+
template <>
-struct Result<RiscvISA::SEWorkload::SyscallABI, SyscallReturn>
+struct Result<RiscvISA::SEWorkload::SyscallABI64, SyscallReturn>
+{
+ static void
+ store(ThreadContext *tc, const SyscallReturn &ret)
+ {
+ if (ret.successful()) {
+ // no error
+ tc->setReg(RiscvISA::ReturnValueReg, ret.returnValue());
+ } else {
+ // got an error, return details
+ tc->setReg(RiscvISA::ReturnValueReg, ret.encodedValue());
+ }
+ }
+};
+
+template <>
+struct Result<RiscvISA::SEWorkload::SyscallABI32, SyscallReturn>
{
static void
store(ThreadContext *tc, const SyscallReturn &ret)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie327b517f41b5d633d2741b6abb5be955281c838
Gerrit-Change-Number: 65532
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang <rogerycch...@google.com>
Gerrit-MessageType: newchange
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