Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/66251?usp=email )
Change subject: arch-arm: Remove deprecated Armv7 debug Vector Catch
......................................................................
arch-arm: Remove deprecated Armv7 debug Vector Catch
This was part of Armv7 self hosted debug and has been officially
deprecated in Armv8
Change-Id: I6ad240ac7dfc389f7de32d4b5b44d9da238c6e46
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/faults.cc
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
3 files changed, 15 insertions(+), 188 deletions(-)
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index b4ef199..379e761 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -503,9 +503,6 @@
void
ArmFault::invoke32(ThreadContext *tc, const StaticInstPtr &inst)
{
- if (vectorCatch(tc, inst))
- return;
-
// ARMv7 (ARM ARM issue C B1.9)
bool have_security = ArmSystem::haveEL(tc, EL3);
@@ -729,20 +726,6 @@
setSyndrome(tc, getSyndromeReg64());
}
-bool
-ArmFault::vectorCatch(ThreadContext *tc, const StaticInstPtr &inst)
-{
- SelfDebug *sd = ArmISA::ISA::getSelfDebug(tc);
- VectorCatch* vc = sd->getVectorCatch(tc);
- if (vc && !vc->isVCMatch()) {
- Fault fault = sd->testVectorCatch(tc, 0x0, this);
- if (fault != NoFault)
- fault->invoke(tc, inst);
- return true;
- }
- return false;
-}
-
ArmStaticInst *
ArmFault::instrAnnotate(const StaticInstPtr &inst)
{
diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc
index 27064cd..a4e685f 100644
--- a/src/arch/arm/self_debug.cc
+++ b/src/arch/arm/self_debug.cc
@@ -56,9 +56,7 @@
if (mode == BaseMMU::Execute) {
const bool d_step = softStep->advanceSS(tc);
if (!d_step) {
- fault = testVectorCatch(tc, req->getVaddr(), nullptr);
- if (fault == NoFault)
- fault = testBreakPoints(tc, req->getVaddr());
+ fault = testBreakPoints(tc, req->getVaddr());
}
} else if (!req->isCacheMaintenance() ||
(req->isCacheInvalidate() && !req->isCacheClean())) {
@@ -368,10 +366,6 @@
const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
setenableTDETGE(hcr, mdcr);
-
- // Enable Vector Catch Exceptions
- const DEVID dvid = tc->readMiscReg(MISCREG_DBGDEVID0);
- vcExcpt = new VectorCatch(dvid.vectorcatch==0x0, this);
}
bool
@@ -706,122 +700,4 @@
return res;
}
-Fault
-SelfDebug::testVectorCatch(ThreadContext *tc, Addr addr,
- ArmFault *fault)
-{
-
- setAArch32(tc);
- to32 = targetAArch32(tc);
- if (!isDebugEnabled(tc) || !mde || !aarch32)
- return NoFault;
-
- ExceptionLevel el = (ExceptionLevel) currEL(tc);
- bool do_debug;
- if (fault == nullptr)
- do_debug = vcExcpt->addressMatching(tc, addr, el);
- else
- do_debug = vcExcpt->exceptionTrapping(tc, el, fault);
- if (do_debug) {
- if (enableTdeTge) {
- return std::make_shared<HypervisorTrap>(0, 0x22,
-
ExceptionClass::PREFETCH_ABORT_TO_HYP);
- } else {
- return std::make_shared<PrefetchAbort>(addr,
- ArmFault::DebugEvent, false,
- ArmFault::UnknownTran,
- ArmFault::VECTORCATCH);
- }
- }
-
- return NoFault;
-}
-
-bool
-VectorCatch::addressMatching(ThreadContext *tc, Addr addr, ExceptionLevel
el)
-{
- // Each bit position in this string corresponds to a bit in DBGVCR
- // and an exception vector.
- bool enabled;
- if (conf->isAArch32() && ELIs32(tc, EL1) &&
- (addr & 0x3) == 0 && el != EL2 ) {
-
- DBGVCR match_word = 0x0;
-
- Addr vbase = getVectorBase(tc, false);
- Addr vaddress = addr & ~ 0x1f;
- Addr low_addr = bits(addr, 5, 2);
- if (vaddress == vbase) {
- if (ArmSystem::haveEL(tc, EL3) && !isSecure(tc)) {
- uint32_t bmask = 1UL << (low_addr + 24);
- match_word = match_word | (DBGVCR) bmask;
- // Non-secure vectors
- } else {
- uint32_t bmask = 1UL << (low_addr);
- match_word = match_word | (DBGVCR) bmask;
- // Secure vectors (or no EL3)
- }
- }
- uint32_t mvbase = getVectorBase(tc, true);
- if (ArmSystem::haveEL(tc, EL3) && ELIs32(tc, EL3) &&
- isSecure(tc) && (vaddress == mvbase)) {
- uint32_t bmask = 1UL << (low_addr + 8);
- match_word = match_word | (DBGVCR) bmask;
- // Monitor vectors
- }
-
- DBGVCR mask;
-
- // Mask out bits not corresponding to vectors.
- if (!ArmSystem::haveEL(tc, EL3)) {
- mask = (DBGVCR) 0xDE;
- } else if (!ELIs32(tc, EL3)) {
- mask = (DBGVCR) 0xDE0000DE;
- } else {
- mask = (DBGVCR) 0xDE00DEDE;
- }
- DBGVCR dbgvcr = tc->readMiscReg(MISCREG_DBGVCR);
- match_word = match_word & dbgvcr & mask;
- enabled = match_word != 0x0;
- // Check for UNPREDICTABLE case - match on Prefetch Abort and
- // Data Abort vectors
- ExceptionLevel ELd = debugTargetFrom(tc, isSecure(tc));
- if (((match_word & 0x18001818) != 0x0) && ELd == el) {
- enabled = false;
- }
- } else {
- enabled = false;
- }
- return enabled;
-}
-
-bool
-VectorCatch::exceptionTrapping(ThreadContext *tc, ExceptionLevel el,
- ArmFault* fault)
-{
- if (conf->isAArch32() && ELIs32(tc, EL1) && el != EL2) {
-
- DBGVCR dbgvcr = tc->readMiscReg(MISCREG_DBGVCR);
- DBGVCR match_type = fault->vectorCatchFlag();
- DBGVCR mask;
-
- if (!ArmSystem::haveEL(tc, EL3)) {
- mask = (DBGVCR) 0xDE;
- } else if (ELIs32(tc, EL3) && fault->getToMode() == MODE_MON) {
- mask = (DBGVCR) 0x0000DE00;
- } else {
- if (isSecure(tc))
- mask = (DBGVCR) 0x000000DE;
- else
- mask = (DBGVCR) 0xDE000000;
- }
- match_type = match_type & mask & dbgvcr;
-
- if (match_type != 0x0) {
- return true;
- }
- }
- return false;
-}
-
} // namespace gem5
diff --git a/src/arch/arm/self_debug.hh b/src/arch/arm/self_debug.hh
index 5ad0d09..069df24 100644
--- a/src/arch/arm/self_debug.hh
+++ b/src/arch/arm/self_debug.hh
@@ -239,48 +239,12 @@
}
};
-class VectorCatch
-{
- private:
- bool vcmatch;
- SelfDebug *conf;
- std::vector<Fault *> vectorTypes();
-
- public:
- VectorCatch(bool _vcmatch, SelfDebug* s) : vcmatch(_vcmatch), conf(s)
- {}
-
- bool addressMatching(ThreadContext *tc, Addr addr, ExceptionLevel el);
- bool exceptionTrapping(ThreadContext *tc, ExceptionLevel el,
- ArmFault* fault);
-
- bool isVCMatch() const { return vcmatch; }
-
- private:
- Addr
- getVectorBase(ThreadContext *tc, bool monitor)
- {
- if (monitor) {
- return tc->readMiscReg(MISCREG_MVBAR) & ~0x1F;
- }
- SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
- if (sctlr.v) {
- return (Addr) 0xFFFF0000;
- } else {
- Addr vbar = tc->readMiscReg(MISCREG_VBAR) & ~0x1F;
- return vbar;
- }
- }
-
-};
-
class SelfDebug
{
private:
std::vector<BrkPoint> arBrkPoints;
std::vector<WatchPoint> arWatchPoints;
SoftwareStep * softStep;
- VectorCatch * vcExcpt;
bool enableTdeTge; // MDCR_EL2.TDE || HCR_EL2.TGE
@@ -294,7 +258,7 @@
public:
SelfDebug()
- : softStep(nullptr), vcExcpt(nullptr), enableTdeTge(false),
+ : softStep(nullptr), enableTdeTge(false),
mde(false), sdd(false), kde(false), oslk(false)
{
softStep = new SoftwareStep(this);
@@ -303,7 +267,6 @@
~SelfDebug()
{
delete softStep;
- delete vcExcpt;
}
Fault testDebug(ThreadContext *tc, const RequestPtr &req,
@@ -318,8 +281,6 @@
Fault triggerWatchpointException(ThreadContext *tc, Addr vaddr,
bool write, bool cm);
public:
- Fault testVectorCatch(ThreadContext *tc, Addr addr, ArmFault* flt);
-
bool enabled() const { return mde || softStep->bSS; };
inline BrkPoint*
@@ -445,12 +406,6 @@
return softStep;
}
- VectorCatch*
- getVectorCatch(ThreadContext *tc)
- {
- return vcExcpt;
- }
-
bool
targetAArch32(ThreadContext *tc)
{
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6ad240ac7dfc389f7de32d4b5b44d9da238c6e46
Gerrit-Change-Number: 66251
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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